Re: AHDL, VERILOG or VHDL??

Hi Hendra,

Hope you won't mind my providing some clarification regarding availability of ModelSim from Altera. Your post suggested we don't provide ModelSim, when in fact we do.

At Altera, one way we provide our software development tools is through the Altera Subscription program (more details at

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and
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In addition to our Quartus II software development tool, this subscription *does include* an Altera-only version of ModelSim.

The second way we provide our tools is through our free Web Edition version of Quartus II. This version is identical to our Subscription Edition, with the exception of a few software features and device support for our high density FPGAs and HardCopy structured ASIC. This version, however, does not include ModelSim. Quartus II (both Subscription and Web Editions) does include a graphical waveform simulator, which sees a lot of use from our customers.

I'm not aware of any FPGA vendor that provides 3rd party simulation tools along with the free version of their software.

There's a couple places to check out to learn more about design simulation with Altera: 1) is our Online Demo Center

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on simulation in the "Basic FPGA/CPLD Design" chapter; and 2) Our Quartus II Handbook contains a nice chapter on simulating with ModelSim (Volume 3, Chapter 1 at
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I hope this has been useful.

Cheers, Chris Balough Director, Software & Tools Marketing, Altera

> Hendra, > > > > You're just too young. :-) MaxPlus II was a rock'n tool for its time. > > And what year was it? > > > Very > > well received by the engineering community. > > At that time may be! But why bother using outdated tool while you can have a > better one? > I don't mind using Altera FPGAs, but the tool must be something other than > MaxPlus II or Quartus. I just don't like any tool from any vendor that does > not support testbench. Specifying your inputs by dragging your mouse instead > of writing a code is just dumb! It may work for very small design, but for > large design, it won't work! To my knowldege, due to the nature of > synthesis, none of the synthesis tool supports testbench, including Xilinx > XST. But Xilinx allows me to use their free ModelSim simulator to be > incorperated with their synthesis tool. While Altera, from my understanding, > doesn't have the free version of their ModelSim. > > Hendra
Reply to
Chris Balough
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I quoted my previous message: " While Altera, from my understanding, doesn't have the free version of their ModelSim."

My post suggested that Altera does not provide the FREE version of ModelSim. It does not say that Altera does not provide the paid version of ModelSim.

Which means unlike Xilinx, Altera does not provide the free version of ModelSim.

Does Quartus Web Edition support VERILOG BASED testbenches? By testbenches I mean I write a program in Verilog that injects signal to the Unit Under Test (UUT). I know MaxPlus II doesn't support it because in order to test my circuit, I have to drag the mouse in the waveform or specify the signal in a text file without any support of loop, or any other data manipulation technique (such as self checking testbench) commonly found in programming language.

Xilinx does provide the free version of ModelSim along with the free Xilinx Webpack.

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for the free Xilinx Webpack
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for the free version of ModelSim Xilinx Edition

Note: the common misconception about the free version of ModelSim Xilinx Edition is the software stops working after 500 lines of code. That is not true! The software still works after 500 lines of code, it just run slower but still works.

Hendra

Reply to
Hendra Gunawan

Hi Chris, An earlier poster in this thread made this claim

".. AHDL is being abandoned even by Altera's newer tools."

Can you comment on that ? AHDL will/does support MAX II, for example ?

I know designers who use AHDL, and find it very productive in the CPLD space, and there must be large numbers of legacy designs coded in AHDL out there.

-jg

Reply to
Jim Granville

Ahhh, but in marketing speak it does. If you buy a subscription for the Altera software you get ModelsimAE thrown in free :-)

BTW the ModelsimAE is slightly slower than the full version but not as knobbled as ModelsimXE.

Nial

Reply to
Nial Stewart

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Hi Jim,

Altera will continue to support AHDL for the foreseeable future in Quartus II. Not only for existing devices, but for any new devices we introduce, such as Max II

Chris

Reply to
Chris Balough

Jim,

You are correct, many designers use AHDL, specially for simple, CPLD type designs. Some use it even for large FPGAs (at least for portions of it).

We probably still have IP written in AHDL.

And if nobody else, we still use it internally for many many of our regression tests.

There is no benefit in removing a widely used, very stable feature (that also has good name recognition). I am sure it will be years before we even consider removing it.

AHDL is basically a family independent language and therefore, supports all of our device families. Therefore, it works just as well for MAX7000B, MAX II, or even Stratix II.

-David Karchmer Altera Corp.

Reply to
David Karchmer

Hi Jim,

Two of Altera's newer tools, SOPC Builder and DSP Builder, do not support AHDL, either for importing or generation. Quartus and Max Plus II definitely still support it.

-- Pete

Reply to
Peter Sommerfeld

I am too (JurAsic), but not AHDL but HDL from Inmos ( a really great but proprietary in house structural HDL developed in 80 with many features Verilog is just now getting).

Now you are asking to be flamed and accused of witchcraft. Truth is its not so difficult to use C with Verilog (or others). For 1 clock domain all digital, its a lifesaver for rapid 1M cycle sims. But for many N clock designs not so digital, it may well be more trouble than its worth. You can use SystemC for high level modelling but not HW synthesis.

regards

johnjakson_usa_com

Reply to
john jakson

Why the hell would you want to? Its not even that good a language for writing software in.

Cheers, JonB

Reply to
Jon Beniston

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