Re: Actel Designer: how to compile VHDL top & EDIF submodule together?

Hello Marek,

Can you explain what you exactly did in your design, so you succefully can compile a VHDL with an EDN file?

I have an edn top design, created by presicion, and a UART VHDL core of Actel, which I need to complie them both in my design.

Thank you in advanced,

Moran.

Hello, Daniel, > >> There are some challenges in merging EDIF netlists with Designer upon >> import. I would let Synplify do the merging for you. Just have your >> netlist in VHDL format and add it as an other source file. You can use >> the edn2vhdl tool to create the VHDL netlist. > >thank you for your answer. This is the problem: I need to bypass >synthesis step, since I am afraid, that some evil optimization could >damage my design. Even if it would work one, I have no guarantee, that >in next Synplify release it will result in exactly the same output >netlist. > >However, I have been told the solution by Actel technical support, so >I am forwarding the reply: >----- >From snipped-for-privacy@microsemi.com Tue Jan 4 10:51:54 2011 >Date: Tue, 4 Jan 2011 15:21:54 +0530 >From: "Gosavi, Sagar" >To: Marek Peca >Subject: RE: Actel Designer: how to compile VHDL top & EDIF submodule >together?: >489394-344304373 > >Hi Marek, > >Thanks for contacting Actel Tech Support. > >Can you please send me the design files for this project so that I >can understand the scenario better? > >Between, if I understand the situation; are you observing some errors >like: > >Error: CMP002: Net: CNT_16[0] is not driven >Error: CMP002: Net: CNT_16[1] is not driven >Error: CMP002: Net: CNT_16[2] is not driven >Error: CMP002: Net: CNT_16[3] is not driven > >Also, if you find syn_black_box in your top level edn, kindly replace >it with the instance name of your subcircuit edn. > >Note: The library name, cell name and the view name of the lower >level cell/edn has to match in its instantiation in the upper (in >this case, the top level) level > >If above solution doesn't help, please send me your Project, so that >I can debug this issue better. > >Have a great day ahead! > >Thanks and Regards, >Sagar Gosavi >----- > >So I have changed the library name to "work" and view name to >"syn_black_box" and now it works as expected, the Designer now >produces reasonably looking composite netlist. The EDIF excerpt looks >like: > > (library work > (edifLevel 0) > (technology (numberDefinition)) > (cell my_strange_circuit > (cellType GENERIC) > (view syn_black_box (viewType NETLIST) > >...etc. > > >Greetings, >Marek >

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