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Re: 5 volt tolerant Xilinx parts

Cypress is anyway getting out of the PLD business...

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Marc Randolph wrote: > > > > > I have been given a very good price on the Coolrunner XCR3512XL, but > > > even with 512 macrocells, including small FIFOs (8 bits x 16 words,

two

> > FIFOs) uses up half the chip. > > ^^^^^^^^^^^^^ > > Unless the design is complete and you can verify that it fits AND you > > have a pinout, this would scare the hell out of me. I have to admit > > not having used the Coolrunnner, but over the past six years, we have > > had an absolutely horrible time making very minor changes to > > moderately full 95xxx series Xilinx CPLD's. Again, this may not apply > > as much to the Coolrunner, since it is a completely different family - > > but I'd still verify it first. > > > > I agree with the other poster - what about the Cypress or Lattice > > devices? I realize that gets you away from your "all Xilinx" board, > > but is there really a good reason for desiring that (except maybe you > > can get all parts from one distributor)? > > No, sticking with Xilinx is not a strong desire since the software is > not common anyway. But Lattice has nothing that will fit this socket > and I have not been able to get a decent price on a Cypress part. I > guess that is also part of my goal to use Xilinx. I have gotten some > really great pricing on the parts I have discussed with them. They are > working with me, so it makes me want to work with them. > > But I agree that using the XCR3512XL is scaring me as well. That is why > I am asking about other Xilinx alternatives. > > I am sure I looked at the Cypress parts. I need about 170+ IOs in a 256 > FBGA. The insides are not real important since that many IOs almost > always means a larger part than what I need, say 20,000 gates or 1000 > LUT/FF. The memory is optional since with that many FFs I can make my > own FIFOs easily. Any idea of what a real price in a Cypress part would > run? I don't really see much that will fit the socket unless I am > missing something. > > -- > > Rick "rickman" Collins > > snipped-for-privacy@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL
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> 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX
Reply to
Neeraj Varma
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Nearly. They ARE getting out of SPLD, and older process CPLD devices.

-jg

Reply to
Jim Granville

Rick,

My point exactly. If you simulate a TTL driver, you will note it can't pull up enough to violate our spec, and so no resistor is required.

Of course, it has to be a TTL driver, and not a CMOS driver!

Now given anyone can build a pcb and sell it, I would go with the TI, or Quickswitch NMOS pass-gate voltage limiter part to be safe (and 100% compatible).

Aust> Aust> >

outlined

Reply to
Austin Lesea

Anything is possible,

But you can't use 90nm for 5V. The minimum size you can use is .35u.

A combo 90 nm/ .35u process is not in the roadmap, so that makes life a bit tough.

But then again, where is the $?

Peter and I are engineers, not marketeers, so we defer to the marketing folks who seem to know just how large (small) the 5V market is....

Aust> Peter, Austin,

Reply to
Austin Lesea

At what process size does the 3.3 volt compatibility go away?

I have never understood why the voltage is a problem. I understand that the thin oxide for the gate will not take the voltage. But I don't see why the IO transistors can't be made with thicker oxides. All chips have thick oxides all over the chip on many layers for isolation. Seems pretty simple to add one more oxide layer for the IO transistor gates.

I understand that this will slow the chip IO a bit and may add a bit of cost, but it is no technical hurdle and 5 volt is still a market. To be able to address the 5 volt sockets in addition to the regular market seems to be a win-win.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX
Reply to
rickman

Austin Lesea wrote: ...

: If you havce 90nm/.35u (no reason why it can't be done), you lose all your : speed and area by having to drive the huge .35u transistors (makes for a : more expensive die).

Austin,

just for interest, is there any document showing the schematics of such a mixed voltage output stage? I think driving the PMOS of the output stage is quite tricky, without sacrificing to much current.

Bye

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply to
Uwe Bonnes

Are you saying that you lose all of the speed and area over the whole die or just for the IO section? If it's just the IO that would be OK in a part like this. A part aimed at the 5V interface market doesn't need fast IOs because the clock rates in that world are low. It does need the logic and RAM density of a modern part, if it wasn't any denser than an old .18u part then you might as well stick with the older part or live with external level shifting transceivers.

Reply to
B. Joshua Rosen

Uwe,

Circuits to do this are considered proprietary.

I could do a search on google for level shifters, but you can, too.

Aust> Aust> ...

Reply to
Austin Lesea

This is left as an exercise for those who already know how to design these circuits,

If you don't, then it is not my place to instruct.

Aust> >

Reply to
Austin Lesea

Austin Lesea wrote: : Uwe,

: Circuits to do this are considered proprietary.

: I could do a search on google for level shifters, but you can, too.

The basic concept is clear for me. An Open Collector/OpenDrain as switch and a pullup resistor ( in the discret case) or a depletion NMOS( in the integrated case) as load. But to get that at speed at low current ...

Bye

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply to
Uwe Bonnes

Acutally Lattice does have parts larger that the XCR3512XL. If you are looking for 256 fpBGA you can get up 768 macrocells in that package using their ispXPLD family. Not only that but each logic block can alternately be made into a large memory element so you will have plenty of room to spare.

Reply to
John Dimtsios 

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX
Reply to
rickman

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