Hello,
I have a design in a Virtex2 that uses RAMB16 primitives. In this design I access to this memory to write and read the same address at the same time. This gives a collision but over the board it has the expected result, it means, it write the data and put in the output the new data. Porting this design to a Virtex4 I found that the behaviour of the RAMB16 is different and the design doesnt work. I go around this problem adding some logic to avoid collisions in the memory. But my question is, is there any difference between RAMB16 primitive in Virtex2 and Virtex4?
Regards
Javier