I am developing a Xlinx Virtex 4 FPGA system and require to change a pcore frequently during the development phase. Whenever I modify the pcore, I have to clean the netlist in EDK and resynthesize/reroute the entire hardware design. This takes a lot of time. Is there any way to just synthesize/place 'n route the modified pcore as opposed to the entire hardware design.
You can specify in the MPD of pcore under development.
OPTION CORE_STATE = DEVELOPMENT
This forces platgen to re-synthesize the pcore on ever iteration. So, need to clean.
For place-route, you'll need to follow the documents regarding incremental place-route.
You can skip the setup for > I am developing a Xlinx Virtex 4 FPGA system and require to change a
As an alternative to the "official" method mentioned by Paulo, another way to trigger a recompile of a single core is to do: rm -f implementation/my_core.ngc rm -f implementation/cache/my_core.ngc Those are Unix(Linux) commands, but I am sure something similar exists under Windows ;)
If you are really ambitious, you can modify the makefiles so that this step is automatically handled by the make system whenever a source file changes.
For example, I have a added to system_incl.make: MY_DDR_CLOCKS_IMPLN = implementation/my_ddr_clocks_wrapper.ngc MY_DDR_CLOCKS_FILES = pcores/ddr_clocks_v1_00_a/hdl/vhdl/ddr_clocks.vhd \ ... (additional files deleted)
MY_DIMM_IMPLN = implementation/my_dimm_wrapper.ngc MY_DIMM_FILES = pcores/plb_dimm_v1_11_a/hdl/vhdl/clock_gen.vhd \ ... (additional files deleted)
MY_REGS_IMPLN = implementation/my_regs_wrapper.ngc MY_REGS_FILES = pcores/plb_regs_v1_00_a/hdl/vhdl/regs_core.vhd \ pcores/plb_regs_v1_00_a/hdl/vhdl/plb_ipif_ssp1.vhd \ pcores/plb_regs_v1_00_a/hdl/vhdl/plb_regs.vhd \ pcores/plb_regs_v1_00_a/data/plb_regs_v2_1_0.mpd \ pcores/plb_regs_v1_00_a/data/plb_regs_v2_1_0.pao
MY_WRAPPER_NGC_FILES = $(MY_DDR_CLOCKS_IMPLN) \ $(MY_DIMM_IMPLN) $(MY_BITS_IMPLN)
MY_DEVELOPMENT_FILES = $(MY_DDR_CLOCKS_FILES) \ $(MY_DIMM_FILES) $(MY_REGS_FILES)
And then to system.make I have inserted: ################################################################# # HARDWARE IMPLEMENTATION FLOW #################################################################
$(MY_DDR_CLOCKS_IMPLN): $(MY_DDR_CLOCKS_FILES) rm -f implementation/my_ddr_clocks_wrapper.ngc rm -f implementation/cache/my_ddr_clocks_wrapper.ngc
$(MY_DIMM_IMPLN): $(MY_DIMM_FILES) rm -f implementation/my_dimm_wrapper.ngc rm -f implementation/cache/my_dimm_wrapper.ngc
$(MY_REGS_IMPLN): $(MY_REGS_FILES) rm -f implementation/my_regs_wrapper.ngc rm -f implementation/cache/my_regs_wrapper.ngc
implementation/$(SYSTEM).bmm \ $(CORE_WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \ ...
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.