Quick question for an Altera wizard

I have a verilog design on Spartan 3 which needs to move to Cyclone II.

The design has 7 128x1 bit asynchronous ROMs using ROM128X1 primitives (this is called distributed ROM?).

Does Cyclone II have something similar? what is the primitive and initialisation syntax?

If not will I have to use an lpm_rom megafunction and burn M4K blocks? The ROMs have common addressing so after some hassle rearranging the initialisation data I could use a single 128x7 bit ROM or after some hassle rearranging the design and initialisation data a 896x1 bit ROM.

TIA

Reply to
nospam
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How about using generic verilog constructs instead? Using primitives is only going to be a source of headaches when used for no particular reason as FPGA architectures evolve and designs need to be ported across device families or vendors.

Simply create an array of 7bits elements, initialize it to whatever your ROM's content has to be and use an index to access it. Pretty much any FPGA synthesis tool worth anything will be able to figure these out and do a satisfactory job in 99% of cases.

I only use primitives for stuff that cannot be inferred. The other defendable reasons to use primitives is for timing-critical and space-critical logic/paths. That aside, I think they should be avoided.

Reply to
Daniel S.

I can send you code that makes a nice fifo out of SRL16s on a Xilinx part (via inference, not with the coregen) and a huge mishmash of flops on an Altera part... If you use 10% of your FPGA you can be content to use perfectly portable source code. If you really need the best speed and density, you're stuck with generated modules that sometimes don't map well to other architectures.

--
Ben Jackson AD7GD

http://www.ben.com/
Reply to
Ben Jackson

I'd be interested in it if you don't mine

KJ

Reply to
KJ

I'd be interested in it if you don't mind.

KJ

Reply to
KJ

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