quick question

I think your equivalent should be: input[x*(y)-1: x*(y)-y+1]

If I remember correctly, the width has to be a constant. In this case that would mean y could be a parameter, but not an integer or register.

-Kevin

The y that follows the indexed part select operator is the width. The vector mk showed has a width of y bits which is accurate. The vector Kevin showed has a width of y-1 bits which is inaccurate. Use mk's suggestion.

Oh, and invest in a Verilog-2001 reference.

Also - I removed the cross-post to comp.lang.vhdl because this is VERILOG! The VHDL abbreviations doesn't mean "Verilog Hardware Description Language." You can go to comp.lang.verilog for Verilog issues.

- John_H

es.

Thanks always for your valuable help.