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Questions about pci transactions in my core

I wrote pci core and implemented it on a virtex 4 fpga, the pci core served as a slave. Now the config space can be read by host bridge correctly, but there are still some questions confusing me. I wish someone here could give me advices, thanks

  1. This pci core doesn't support burst transaction. so signal TRDY was designed to be valid for one cycle and then set to 1. the problem is in a read transaction, the master device didn't get any data during this cycle though the IRDY is low. why? however, if the TRDY delayed for one cycle, that is it was valid for two cycles, the master can read data correctly.

  1. In a write configuration transaction(eg: writing "FFFFFFFF" into memory base address DWORDs), there should be some 0s in the Byte Enable signal. but the fact was BE=1111, no byte was written. why the host gave such a BE?

thanks all

Reply to
Perry
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Did it get no data or did it get the wrong data (eg. 0)?

I guess you output your data one clock cycle late. Or you did not tell the master to finish the cycle. If the master wants to burst and the slave does not agree it must do a target abort. (stop='1' IIRC)

Kolja Sulimma

Reply to
comp.arch.fpga

Depending on what is happening you may want to assert a terminate with data (STOP + TRDY) if the cycles is trying to burst. On the byte enables you will see many apparently strange things happening on PCI and you need to follow the entire cycle and decode fully what it means. Shortcuts in decode will lead to problems invariably.

John Adair Enterpo> I wrote pci core and implemented it on a virtex 4 fpga, the pci core

Reply to
John Adair

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