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question regarding "Add I/O buffers" option - SOS

Hi ppl,

I previously asked something similar. The thing is that I am integrating a design of somebody who's been using schematic design capture and his design is delivered in a generated VHDL code (or NGC as well).

Now, the delivered design has already IBUFs / OBUFs inside, whereas my high-level code (the top module) does not. Consequently, I cannot do AND between two dsesigns, one with and one without IBUFs / OBUFs. If I turn on "Add I/O Buffers" option, I get an error, as the buffers are trying to be driven by another buffers inferred by the tool. If I turn off "Add I/O Buffers" option, all the logic is removed form design, as LOC constraints on the pins cannot be applied, because no buffers are inferred.

As far as I understand the situation I have two choices: (*) I design this core by myself. (*) I manually add IBUFs / OBUFs in the top module and try synthesizing with "Add I/O Buffers" option turned off.

Is there a way to enable / disable the option "Add I/O Buffers" in Xilinx per module / block? Is there a way to overcome this problem?

Thank you all for your time and attention

Sincerely, Vladislav

Reply to
Vladislav Muravin
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No. The Add I/O buffers only really affects the top level module anyway. If you need more control, turn it off and instantiate all your I/O buffers (IBUF, IBUFG, OBUF, ughh...).

Yes. When you want to use another design as a black box, it should be built without IO buffers. Only the top level design should have IO buffers. Therefore you need two projects, one to build the black box (in your case a schematic project) with add I/O buffers turned off. You don't need to translate / map / place / route this project, just "synthesize" (yes there's HDL under the hood of ECS schematics) to create the ngc file.

The second is your top level project (HDL in your case) with Add I/O Buffers turned on. In this project you create an empty HDL module with the i/o list from the schematic. If the schematic module connects to pins, you'll need to add the connections from this module to the pins in your HDL top-level code.

Then just move the ngc file from the schematic project to the synthesis directory (project directory) of the HDL project. Make sure the base filename is the same as the module name in your HDL. XST will not try to synthesize your empty HDL module, but will insert the compiled ngc into the top level design.

Reply to
Gabor

Dear Gabor,

Thank you very much for your response. Actually, what you've said was the first thing i have asked before agreeing to accept this kind of project. But this never was met with enthusiasm... Managers stuff...

I am going to try manual instantiation of ~300 I/O buffers... Good luck to me.

Vladislav

Reply to
Vladislav Muravin

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