Greetings,
First off, let me share with you that I'm a complete newb when it comes to FPGA/ISE/VHDL. I'm using the "free" version of ISE and my end device is a V2P-7 672 pin FPGA with the pins already locked and unchangable on a custom board. I'm using VHDL.
The issue I'm trying to deal with is deserializing an 8 bit serial line from a clock rate of 1MHz upto 40MHz (bit rate of 8MHz to 320MHz) with the ability to switch which incoming clocks to use as the master deserializer clock. The deserializer I'm using is a portion of XAPP265 from XILINX, mainly just the flipflop section (not the block ram or DCM section).
The first problem is the wide range of clock rates I need to program for. The 2nd issue deals with the fact that the "SYNC" clock may be unstable depending on the DUT and I will want to switch to a secondary SYNC clock if that's the case. The 2nd problem is how to implement the DCMs using as few of them as possible.
The following is a description of the FPGA inputs: These 2 signals come directly from the DUT SYNC - The 1MHz to 40MHz clock from the device under test (DUT) which can sometimes be unstable INPUT - The 8MHz to 320MHz data word which I want to deserialize These 2 signals come from a clock generator which can be used in place of the SYNC if the SYNC clock is too unstable for deserializing PCLK - Optional 1MHz to 40MHz clock from external clock generator to be used instead of SYNC if necessary (on different pins from SYNC). CLK4x - Optional 4x of PCLK clock which is used as a DDR clock to deserialize data from INPUT if SYNC is too unstable
Here is my current approach: If the DUT is operating at slow speeds (SYNC < 24MHz), I use the CLK4x input as my DDR clock because the DCM can't generate the 4x clock from the SYNC clock. I may optionally switch out the SYNC clock for the PCLK if the SYNC clock is too unstable. This is currently one build of the FPGA code and it appears to work fine. No DCMs are used in this build.
My next approach is to figure out how to combine the slow and high speed options but am not sure the best way to approach this. I want to have a command protocol between my computer and the FPGA to be able to tell the FPGA if the DUT will be operating in SLOW or HIGHSPEED mode and command which clock, SYNC or PCLK to use.. HIGHSPEED mode will first try to use the SYNC clock and generate a 4xSYNC clock to use as the DDR clock, but if that fails due to SYNC instability, use the PCLK in place of the SYNC.
I'm thinking I need at least 2 DCMs to do this. One to phase shift the SYNC/PCLK signal since I can't get the PCLK to have 0 phase relation with the SYNC clock externally and another DCM to generate a phase shiftable 4x clock from the SYNC/PCLK clock. I'm thinking of using a mux to switch between PCLK and the SYNC clock to the input of the both DCMs and a mux to switch in either the external CLK4x or the DCM generated CLK4x to operate as the DDR clock.
Will this approach work? Is there a better way to do this? How can I tell the DCM which frequency it'll be operating at (the DCM pixel period generic) and is that generic really necessary?
Thanks, Jason