Hi,
I am new using Xilinx EDK. The version I'm using is 6.3.
I'd like to access OPB bus from PCI side. I'm Xilinx OPB/PCI bridge v3 in a project where I'm using custom board. Linux and Windows are able to recognize the PCI bridge and does allocate resources but unable to access to the device on the OPB bus.
Please have a look at my mhs file, and advise me if I have done something wrong!
Thank you in advance. Riz/
Here is my mhs file;
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PARAMETER VERSION = 2.1.0
PORT sys_rst = sys_rst, DIR = IN PORT clk_40mhz = clk_40mhz, DIR = I, SIGIS = CLK PORT SDRAM_WEn = opb_sdram_0_SDRAM_WEn, DIR = OUT PORT SDRAM_RASn = opb_sdram_0_SDRAM_RASn, DIR = OUT PORT SDRAM_DQM = opb_sdram_0_SDRAM_DQM, VEC = [0:3], DIR = OUT PORT SDRAM_DQ = opb_sdram_0_SDRAM_DQ, VEC = [0:31], DIR = INOUT PORT SDRAM_Clk = opb_sdram_0_SDRAM_Clk, DIR = OUT, SIGIS = CLK PORT SDRAM_CSn = opb_sdram_0_SDRAM_CSn, DIR = OUT PORT SDRAM_CKE = opb_sdram_0_SDRAM_CKE, DIR = OUT PORT SDRAM_CASn = opb_sdram_0_SDRAM_CASn, DIR = OUT PORT SDRAM_BankAddr = opb_sdram_0_SDRAM_BankAddr, VEC = [0:1], DIR = OUT PORT SDRAM_Addr = opb_sdram_0_SDRAM_Addr, VEC = [0:11], DIR = OUT PORT RS232_RX = RS232_RX, DIR = I PORT RS232_TX = RS232_TX, DIR = O PORT TRDY_N = TRDY_N, DIR = INOUT PORT CBE = CBE, VEC = [3:0], DIR = INOUT PORT DEVSEL_N = DEVSEL_N, DIR = INOUT PORT FRAME_N = FRAME_N, DIR = INOUT PORT AD = AD, VEC = [31:0 ], DIR = INOUT PORT SERR_N = SERR_N, DIR = INOUT PORT INTR_A = INTR_A, DIR = OUT PORT IRDY_N = IRDY_N, DIR = INOUT PORT PAR = PAR, DIR = INOUT PORT GNT_N = GNT_N, DIR = IN PORT STOP_N = STOP_N, DIR = INOUT PORT RST_N = RST_N, DIR = IN PORT REQ_N = REQ_N, DIR = OUT PORT PERR_N = PERR_N, DIR = INOUT PORT PCLK = PCLK, DIR = IN, SIGIS = CLK PORT IDSEL = IDSEL, DIR = IN
BEGIN microblaze PARAMETER INSTANCE = mblaze PARAMETER HW_VER = 3.00.a BUS_INTERFACE DLMB = d_lmb BUS_INTERFACE ILMB = i_lmb BUS_INTERFACE DOPB = mb_opb BUS_INTERFACE IOPB = mb_opb PORT CLK = clk_40mhz PORT INTERRUPT = net_gnd END
BEGIN lmb_v10 PARAMETER INSTANCE = i_lmb PARAMETER HW_VER = 1.00.a PORT SYS_Rst = sys_rst PORT LMB_Clk = clk_40mhz END
BEGIN lmb_v10 PARAMETER INSTANCE = d_lmb PARAMETER HW_VER = 1.00.a PORT SYS_Rst = sys_rst PORT LMB_Clk = clk_40mhz END
BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = i_bram_cntrl PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00007fff BUS_INTERFACE SLMB = i_lmb BUS_INTERFACE BRAM_PORT = ilmb_port PORT LMB_Clk = clk_40mhz END
BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = d_bram_cntrl PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00007fff BUS_INTERFACE SLMB = d_lmb BUS_INTERFACE BRAM_PORT = dlmb_port PORT LMB_Clk = clk_40mhz END
BEGIN bram_block PARAMETER INSTANCE = bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTB = dlmb_port BUS_INTERFACE PORTA = ilmb_port END
BEGIN opb_pci PARAMETER INSTANCE = pci PARAMETER HW_VER = 1.00.c BUS_INTERFACE MSOPB = mb_opb PARAMETER C_PCI_ABUS_WIDTH = 32 PARAMETER C_PCI_DBUS_WIDTH = 32 PARAMETER C_DEVICE_ID = 0x0300 PARAMETER C_VENDOR_ID = 0x10ee PARAMETER C_REV_ID = 0x00 PARAMETER C_CLASS_CODE = 0x0b4000 PARAMETER C_BASEADDR = 0x08bb9000 PARAMETER C_HIGHADDR = 0x08bb9fff PARAMETER C_INCLUDE_PCI_CONFIG = 0 PARAMETER C_IPIFBAR_NUM = 2 PARAMETER C_IPIFBAR_0 = 0x08d90000 PARAMETER C_IPIF_HIGHADDR_0 = 0x08d9ffff PARAMETER C_IPIFBAR2PCI_0 = 0x0 PARAMETER C_IPIFBAR_1 = 0x08990000 PARAMETER C_IPIF_HIGHADDR_1 = 0x0899ffff PARAMETER C_IPIFBAR2PCI_1 = 0x0 PARAMETER C_PCIBAR_NUM = 1 PARAMETER C_PCIBAR_0 = 0xff600000 PARAMETER C_PCIBAR2IPIF_0 = 0x08000000 PARAMETER C_PCIBAR_LEN_0 = 23 PARAMETER C_PCI_PREFETCH_0 = 1 PARAMETER C_PCI_SPACETYPE_0 = 1 PARAMETER C_PCIBAR_ENDIAN_TRANSLATE_EN_0 = 1 PORT TRDY_N = TRDY_N PORT CBE = CBE PORT DEVSEL_N = DEVSEL_N PORT FRAME_N = FRAME_N PORT AD = AD PORT SERR_N = SERR_N PORT INTR_A = INTR_A PORT IRDY_N = IRDY_N PORT PAR = PAR PORT GNT_N = GNT_N PORT STOP_N = STOP_N PORT RST_N = RST_N PORT REQ_N = REQ_N PORT PERR_N = PERR_N PORT PCLK = PCLK PORT OPB_Clk = clk_40mhz PORT IDSEL = IDSEL END
BEGIN opb_uartlite PARAMETER INSTANCE = uart PARAMETER HW_VER = 1.00.b PARAMETER C_DATA_BITS = 8 PARAMETER C_CLK_FREQ = 40000000 PARAMETER C_BAUDRATE = 9600 PARAMETER C_USE_PARITY = 0 PARAMETER C_ODD_PARITY = 0 PARAMETER C_BASEADDR = 0x08e38000 PARAMETER C_HIGHADDR = 0x08e380ff BUS_INTERFACE SOPB = mb_opb PORT RX = RS232_RX PORT TX = RS232_TX PORT OPB_Clk = clk_40mhz PORT Interrupt = net_gnd END
BEGIN opb_sdram PARAMETER INSTANCE = opb_sdram_0 PARAMETER HW_VER = 1.00.e PARAMETER C_SDRAM_TRAS = 60000 PARAMETER C_SDRAM_TRC = 90000 PARAMETER C_SDRAM_TRFC = 85000 PARAMETER C_SDRAM_TRRD = 25000 PARAMETER C_SDRAM_DWIDTH = 32 PARAMETER C_SDRAM_AWIDTH = 12 PARAMETER C_SDRAM_COL_AWIDTH = 9 PARAMETER C_SDRAM_BANK_AWIDTH = 2 PARAMETER C_OPB_CLK_PERIOD_PS = 19240 PARAMETER C_BASEADDR = 0x08000000 PARAMETER C_HIGHADDR = 0x087fffff BUS_INTERFACE SOPB = mb_opb PORT SDRAM_Addr = opb_sdram_0_SDRAM_Addr PORT SDRAM_RASn = opb_sdram_0_SDRAM_RASn PORT SDRAM_Clk = opb_sdram_0_SDRAM_Clk PORT SDRAM_Clk_in = clk_40mhz PORT SDRAM_CKE = opb_sdram_0_SDRAM_CKE PORT SDRAM_CSn = opb_sdram_0_SDRAM_CSn PORT SDRAM_CASn = opb_sdram_0_SDRAM_CASn PORT SDRAM_WEn = opb_sdram_0_SDRAM_WEn PORT SDRAM_DQM = opb_sdram_0_SDRAM_DQM PORT SDRAM_BankAddr = opb_sdram_0_SDRAM_BankAddr PORT SDRAM_DQ = opb_sdram_0_SDRAM_DQ PORT OPB_Clk = clk_40mhz END
BEGIN opb_v20 PARAMETER INSTANCE = mb_opb PARAMETER HW_VER = 1.10.c PARAMETER C_BASEADDR = 0xfffffe00 PARAMETER C_HIGHADDR = 0xffffffff PARAMETER C_REG_GRANTS = 0 PARAMETER C_PROC_INTRFCE = 1 PORT OPB_Clk = clk_40mhz PORT SYS_Rst = sys_rst END
BEGIN opb_bram_if_cntlr PARAMETER INSTANCE = opb_bram_if_cntlr_0 PARAMETER HW_VER = 1.00.a PARAMETER C_BASEADDR = 0x08b10000 PARAMETER C_HIGHADDR = 0x08b11fff BUS_INTERFACE SOPB = mb_opb BUS_INTERFACE PORTA = bram_block_0_port PORT OPB_CLK = clk_40mHz END
BEGIN bram_block PARAMETER INSTANCE = bram_block_0 PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = bram_block_0_port END