Question about Xilinx ISE (problem with signals trimming)

You didn't say what ther errors were. Normally map only removes logic that will not affect the outputs of the design. Then if you have timing contraints for example on nets that have been trimmed you'll get errors during build. If you really want to keep parts of a design even when they aren't used, you can generate a function from the nets (like a big OR or AND gate) and run its output to an unused pin.

If you're getting errors because map removed portions of the design that are actually used, this often happens because those parts were not sourced for some reason (missing clock connection could cause this). What errors are you actually seeing? Can you post a few lines of the report?

HTH, Gabor

thanks problem solved, it was because as you said problems with clock connections.