Hello,
I have the following VSD (very simple design)
module a2v(clka, clkb); input clka; output clkb; buf b1(clkb,clka); endmodule
I expect the clock input to come out as the output (with a delay or not/whatever) I then goto simulation waveform, and the output changes to 1 and then stays at 1. Any ideas why that would be so?
Some questions:
1) are you saying that clka is toggling in the simulation, but clkb goes high and stays high?2) what simulator?
3) did you look at the simulation model for buf? Are you sure the order of the module ports is correct in your instantiation?
Yes!!!
ISE 8.2 Test Bench Waveform - Generate Expected Simulation
No I didn't look at this, but I believe with and/or/not/buf the convention is output comes before the input.
Hi,
Do not run this flow. This is a flow with Known Issues and that is why Xilinx has removed it in the 9.1i version. Try this in the behavioral simulation flow and see if it works. If it does, then use that flow.
Buf is just a verilog construct. It should not use the simulation model.
Thanks Duth
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