Question about multi write ports RAM in FPGA? - Page 2

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Re: Question about multi write ports RAM in FPGA?
Thank you. I will try it the synthesizer and see the resource usage.


Re: Question about multi write ports RAM in FPGA?
To fpga,
     Do you have any relationship with GN,pheonix. If no sorry for the
trouble.


Re: Question about multi write ports RAM in FPGA?
To John_H
I am a beginer in this type of advanced concepts. I am also facing the
same problem of multiple read port and multiple write port. But i could
not understand the concept in your design. Please explain little bit
more.
Thanks in advance Sumesh


Re: Question about multi write ports RAM in FPGA?
There is a similar trick which used to be tought in CS for how to
exchange 2 registers without using a temp reg. Since xor and mov
usually both take 1 cycle but may not have same effect on CC flags.

A <= A^B; B <= A^B; A <= A^B;

gives the same result as

T <= A; A <= B; B <=T;

If you can get your head around that, then its the same idea on a
bigger scale.

Remember that the valid read value on any top level R port is the ^ of
all 3 ports so any write to that same address must contribute bit
toggles that cancel out twice leaving only the desired data. Assume the
other 2 guys writing data are only writing 0s so in effect write port A
always writes X^0^0 into ram A and the read is going to be X ^ 0 ^ 0
again. If the 2nd guy wrote Y to ram 2 before hand, then change a 0 for
Y on both the write and read for X and it cancels out. Same again for
3rd guy writing Z to port 3. This can go on for more ports but requires
NN Rams.

John Jakson


Re: Question about multi write ports RAM in FPGA?
Quoted text here. Click to load it

Repeating the response to a previous thread which included code:
Quoted text here. Click to load it

Each write port has its own memory associated with it.  When you're
writing to one port since you can't update the others, you have to make
the data "right" independent of which write port was last used.  The XOR
lets your latest input data store into your memory

   MemA[AddrA] <= MemB[AddrA]^MemC[AddrA]^DinA

and retrieve the original data that was written

   RdA = MemA[AddrA]^MemB[AddrA]^MemC[AddrA]
       = (MemB[AddrA]^MemC[AddrA]^DinA) ^ MemB[AddrA]^MemC[AddrA]
       = DinA^(MemB[AddrA]^MemC[AddrA]) ^ MemB[AddrA]^MemC[AddrA]
       = DinA ^ (MemB[AddrA]^MemB[AddrA]) ^ (MemC[AddrA]^MemC[AddrA])
       = DinA ^ 0 ^ 0
       = DinA

You can't touch the other memories for writes but you can access them
for reads allowing you to retrieve the most recently written Din value
from the set of write ports.

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