Question about initializing the ram value in test bench

How do i initialize the ram value in test bench? And how do i read back the value. The following codes is what i have tried but i read back the signal as undefined ("UUUUUUUU"). Can someone help me out?

Thanks in advance.

entity Memory_Unit is Port ( .....); end Memory_Unit;

architecture Behavioral of Memory_Unit is

type mem_type is array(0 to memory_size-1) of STD_LOGIC_VECTOR (word_size-1 downto 0);

signal memory : mem_type; begin process(clk) begin if clk'event and clk = '1' then if r_write = '1' then memory(conv_integer(address))