question about DCM in virtex5: fails the maximum period check

Hello, all

I simulate my design in modelsim and it works fine. But when I put it on board, the result it wrong. I noticed the following warning in the .mrp file complaining about DCM and I don't know what it will affect the result.

The system uses a DCM with "PARAMETER C_CLKDV_DIVIDE = 5.000000" to generated a 20Mhz signal from the input clk pin (100MHz in ML501 xilinx board) and work as the master clock for microblaze. A coprocessor is connected with microblaze and part of the design needs a syncronized 3x clock signals. So I used a DCM to generated the 3 times clock over the master clock. But when I do the implementation, the following warning is given:

My question is:

1, will the mean that the syncronized 3x clock generation failed? Then why it just a warning, but not error? 2, What does it mean and how can I avoid it?

Thanks a lot, Cathy

-------------------------------------------------------------------------------------------- WARNING:Timing:3234 - Timing Constraint "TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLKDV_BUF" TS_sys_clk_pin * 5 HIGH 50%" fails the maximum period check for input clock MB0DLMBCntrl_BRAM_PORT_BRAM_Clk to DCM ...../dcm3_inst/DCM_INST because the period constraint value (50000 ps) exceeds the maximum internal period limit of 20001 ps. Please reduce the period of the constraint to remove this timing failure. WARNING:Timing:3236 - Timing Constraint "TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLKDV_BUF" TS_sys_clk_pin * 5 HIGH 50%" fails the maximum period check for output clock ..../dcm3_inst/CLKFX_BUF from DCM ....t/dcm3_inst/DCM_INST because the period constraint value (16666 ps) exceeds the maximum internal period limit of 10001 ps. Please reduce the period of the constraint to remove this timing failure. WARNING:Timing:3236 - Timing Constraint "TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLKDV_BUF" TS_sys_clk_pin * 5 HIGH 50%" fails the maximum period check for output clock .../dcm3_inst/CLK0_BUF from DCM .../dcm3_inst/DCM_INST because the period constraint value (50000 ps) exceeds the maximum internal period limit of 31251 ps. Please reduce the period of the constraint to remove this timing failure. WARNING:Timing:3234 - Timing Constraint "TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLKDV_BUF" TS_sys_clk_pin * 5 HIGH 50%" fails the maximum period check for input clock MB0DLMBCntrl_BRAM_PORT_BRAM_Clk to DCM ...../dcm3_inst/DCM_INST because the period constraint value (50000 ps) exceeds the maximum internal period limit of 20001 ps. Please reduce the period of the constraint to remove this timing failure. WARNING:Timing:3236 - Timing Constraint "TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLKDV_BUF" TS_sys_clk_pin * 5 HIGH 50%" fails the maximum period check for output clock ....t/dcm3_inst/CLKFX_BUF from DCM ..../dcm3_inst/DCM_INST because the period constraint value (16666 ps) exceeds the maximum internal period limit of 10001 ps. Please reduce the period of the constraint to remove this timing failure. WARNING:Timing:3236 - Timing Constraint "TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLKDV_BUF" TS_sys_clk_pin * 5 HIGH 50%" fails the maximum period check for output clock ..../dcm3_inst/CLK0_BUF from DCM ..../dcm3_inst/DCM_INST because the period constraint value (50000 ps) exceeds the maximum internal period limit of 31251 ps. Please reduce the period of the constraint to remove this timing failure.K0_BUF from DCM ..../dcm3_inst/DCM_INST because the period constraint value (50000 ps) exceeds the maximum internal period limit of 31251 ps. Please reduce the period of the constraint to remove this timing failure.

Reply to
cathy
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You should not drive a DVM with 20 MHz, but you have many alternatives:

Use two DCMs, one to divide 100 MHz into 20 MHz, the other one to convert 100 MHz into 60 MHz. (Simultaneously divide by 5 and multiply by 3)

Or, if you worry about phase coherency: Use one DCM to convert 100 MHz into 60 MHz, use a counter or a second DCM to divide 60 MHz into 20 MHz. Peter Alfke ===========

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Reply to
Peter Alfke

Thank you. I will have try.

Reply to
cathy

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