Do you have a question? Post it now! No Registration Necessary
- Posted on
September 4, 2003, 12:08 pm
rate this thread
Re: question about configue apex20k with ppa scheme
The fact that nSTATUS drives low indicates that the device is
reporting an error in the data that it is receiving. There are many
possible causes to investigate, both software and hardware:
1. Ensure that you are using the appropriate data file. In most cases
you will use a RBF (raw binary file). But if programming a standard
EPROM, you would use HEX. If reading as an ASCII representation of hex
(like an include file for a C program) you would use TTF. If using an
Altera configuration device, you would use POF. You would never
directly use SOF - this is the root file made by Quartus or MAX+PLUS
II from which the other files are made.
2. Check the signal integrity on the board, specifically at the APEX
20K device pins. In most configuration schemes the most important
signal for signal integrity is the DCLK pin, but in PPA the nWS pin
acts as a strobe, so noise on that pin can be a problem.
3. Check the timing of the signals. The configuration information on
www.altera.com includes timing specifications that your system must
meet for the FPGA to successfully receive the data.
This is a start, but there are other possibilities as well. In order
to help designers debug configuration issues, Altera has just released
an "FPGA Configuration Troubleshooter" on our web site, at the
This troubleshooter will ask you various questions about what your
setup is and what you are seeing on the board, and lead you to
possible solutions. I encourage you to try it if the suggestions I
have shown above do not solve the problem.
firstname.lastname@example.org (pkuanfm) wrote in message
- » How to contact the writer of Xilinx FPGA application notes?
- — Next thread in » Field-Programmable Gate Arrays
- » engineered data path versus inferred data path
- — Newest thread in » Field-Programmable Gate Arrays