Question about adder structure

Hi, In the book "Digital signal processing with field programmable gate arrays" (1st edition) written by U.Meyer Baese, I don't understand one sentence. On page 45 about binary adders, it gives:

s_k=x_k XOR y_k XOR c_k;

c_k+1 = (x_k . y_k) + (x_k . c_k) + (y_k . c_k)

In the case of a 2C adder, the LSB can be reduced to a half adder because the carry input is zero.

I don't understand the last sentence. For a not 2C adder, I think the LSB can also be reduced to a half adder because the carry input is zero. Am I wrong? Where is wrong?

Another question, although I did some logic in my work, I was given a question "What is the 2's complement of 011 (binary)? For my deep memory, my answer is 101 (binary). I came this from:

not 011 => 100;
increase 1 => 101. Is it correct?

Thank you very much.

Hi! About the adder Question: The 2level-Combinational Adder (or Fulladder) consists of two half adders and an OR-gate. The reduction to a Half Adder for the LSB is only valid under the assumption that there is no Carry from an earlyer calculation.

For a "not-2C Adder", well, whatever architecture it has if it isn't created from half adders, the LSB can't be reduced to a halfadder without destroying the "not-2C" architecture. (e.g. Carry Look Ahead Adder)

About the 2's complement: It's a cognitive trick: The question was: what IS the 2's complement of 011 (binary)? The 2's complement of 011 (binary) IS 011, because it's a positive number. Remember that the 2's complement number range has a positive part too!

You answered the question: can you create the 2's complement of

-011(binary)? Here it's clear that we have a negative number and can construct it's

2's complement as you did.

In the case of signed numbers always ask about the way of the sign representation. (Sign Bit, 2's complement or some other coding scheme) Only with that additional information you can decide what to do.

Best regards Eilert

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