QuartusII, Flex10K & fan-out

Hello Is there a way to specify a maximum signal fan-out for Altera Flex10K FPGAs? The option seems only be available for more recent families. I am explicitly duplicating high-fanout signals and putting "preserve" constraints but it is long since I don't always know signals fan-out.

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Reply to
Nicolas Matringe
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Hi Nicolas,

The max fan-out feature is available for the families after Flex10K i.e , Apex 20K/E/C/II, Stratix, StratixGX, Cyclone, Stratix II and MaxII. If you are starting a new design the Cyclone device family should support the performance and or features you need.

Hope this helps.

- Subroto Datta Altera Corp.

Reply to
Subroto Datta

This question tells me that you are treading on thin ice with high fan out signals. A few years ago, I worked on adding functions to an existing design in a EP10K100A, IIRC. The original design has a major problem where they suspected a high fanout node was not meeting timing even though the tools said it did. They had to conduct temperature tests on the completed design before they could sign off on it. We ran into the same problem even after we duplicated logic to get rid of the high fan outs. I belive we limited the fan out to something like 20 or less. There is an option in the Max+II software somewhere. If you are using Quartus, you may not have the same problem.

If there is any way, I would recommend that you drop this chip and use a newer one. I expect you are updating an existing design, like we were doing, and you are stuck with the hardware. The other thing is to limit your total LE usage to about 85% and expect routing problems if you have timing restrictions that are at all tight. We found that at 90% full, the chip was almost impossible to route, even with location constraints. I called it the whack-a-mole problem. You arrange a couple of registers to get them to meet timing and a couple more fail... lather, rinse, repeat...

That project used more of my free time than I have ever spent on any personal activity. I will still not use Max+II for a project no matter how much I am paid!!!

One other thought, you might want to use "keep" rather than preserve. I was just reading about that and I don't recall that they do the same thing. "keep" inserts an LE buffer which makes this the output of a logic cell and will not be optimized away, it also uses your signal name in the netlist file. I don't remember what "preserve" does, but I found it would not work for my needs. I am using a lot of keeps in a 1K50 design to obtain optimal logic. The software is just not that good at orgainizing the logic... Opps, I just read up on it and "preserve" is for registers and "keep" is for LEs. Nevermind...

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Rick "rickman" Collins

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rickman

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