I was trying to use the SDRAM controller without using the NIOS. I am now using the vhdl file generated from SOPC builder.
Things are great during simulation i.e. However, when I try to synthesize it. I receive the following warning message:
Warning: Can't pack node sdram_0:sdram_con_inst|m_addr[10] to I/O pin.
+Warning: Can't pack logic cell sdram_0:sdram_con_inst|m_addr[10] and I/O node zs_addr[10] -- logic cell cannot be packed as I/O register +Warning: Can't pack logic cell sdram_0:sdram_con_inst|m_addr[10] and I/O node sdram_0:sdram_con_inst|m_addr[10] -- logic cell cannot be packed as I/O register +Warning: Can't pack logic cell sdram_0:sdram_con_inst|m_addr[10] and I/O node sdram_0:sdram_con_inst|i~28445 -- logic cell cannot be packed as I/O registerThe m_addr[10] ties to the address pin of the RAM. Bits 9 and 8 are the same as well. Can't seem to find out the reason.
I understand that a register is inserted at the pins to optimize timing. If this this node is not packed, does it mean to say that it is bypassed to the pin. In a sentence, how does this impact functionality?
Timing analyzer tests indicate that +ve slack so in the end, timing seems up to scratch.
Thanks for your help! ;->
Ted