Quartus VHDL problem with aggregate and type cast

Here is some code showing a problem I am having with Quartus. Seems using a type cast with an aggregate throws it all off. This is just a simple test case which uses a 16 bit bidir bus to write to an 8 bit register and read it back.

-- VHDL created by Rick Collins Library ieee; Use ieee.std_logic_1164.all; Use ieee.numeric_std.all;

ENTITY Test1 is PORT ( Data : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0); Addr : IN STD_LOGIC_VECTOR (7 DOWNTO 0); CSN : IN STD_LOGIC; RDN : IN STD_LOGIC; WRN : IN STD_LOGIC;

LED : OUT STD_LOGIC;

Reset : IN STD_LOGIC; SysClk : IN STD_LOGIC); -- 50 MHz Clock END Test1;

ARCHITECTURE behavior OF Test1 IS

constant SysClkRate : real := 50000.0; -- Rate in KHz signal ScratchReg : STD_LOGIC_VECTOR (7 downto 0); signal DataOut : STD_LOGIC_VECTOR (15 downto 0); signal ReadScratchReg : STD_LOGIC;

BEGIN

ReadScratchReg 'Z');

-- Data (7 downto 0) 'Z');

-- VERSION 2

-- This line fails by disabling the tristate buffers

-- Data '0') & ScratchReg;

ScratchRegister: process (SysClk, Reset) begin if (Reset = '1') then ScratchReg '0'); elsif (rising_edge(SysClk)) then if (Addr = "00001000") THEN if (WRN = '0' and CSN = '0') THEN ScratchReg