Hi all, We had some strange behaviour with our project today. We have been using Mentor Graphics HDL Maker, ModelSim and Quartus for our university project. The code simulated fine in ModelSim, everything was
perfect. However when synthesised onto the Flex10k device we had everything worked fine except for one signal. We revised our code and retried various approaches all with the same result. Next we combed through the output of the synthesiser to try and find any relevant errors. We had a simple slow speed project so most of the errors were from timing violations. As a last approach, which should probably have been a first approach, we took all of the signals to output pins on the device so we could observe their state. With that simple change in HDLMaker, just adding three more output ports and wiring them up to the existing signals between modules the difficult signal started working. I assume this is something to do with optimisation in the synthesiser. But I don't think it should have done it. Has this happened to anyone else? What can I do to prevent it happening again? Is it because of bad coding style? What errors or warnings does Quartus give when it's done something like
this? Try to take it easy on me, I am a university student but this is for my
own knowledge not any homework question :-) Thanks Joel