Quartus II v4.2 LogicLock Regions

I am trying to get a simple LogicLock region (about 200 LEs) optimized, back annotated and tested. But I am having problems. I am hoping someone can help me out. I am using VHDL files and an entity called mesher in a file named mesher.vhd. I am targeting a Stratix FPGA.

This is what I have done so far: 1) Made a project with mesher as the top level. I set all the ports to virtual pins in the assignment editor, and defined the clock

2) Compiled. 3) Defined the LogicLock Region and dragged the entity mesher into it. Also placed all the virtual IOs into the LogicLock Region. 4) Compiled. 5) Adjusted synthesizer and fitter parameters until I was happy with the fit. 6) Back annotated placement and routing and wrote the .VQM file.

Everything seemed okay, except a few LEs are placed outside the LogicLock region for some of the fitter generated nodes. I don't know why, because there was enough unused LEs inside the LogicLock Region. The nodes place outside were not part of any critical path. How does one get the fitter to place these nodes inside the LogicLock Region?

7) To check if everything would work, I removed my source files from the project files list and entered the .VQM file. 8) I turned off all fitter optimizations. 9) Tried to compile and I got fitting errors.

I would expect this compile to place all node where they were when I back annotated. I would expect the timing to be exactly the same too.

Does anyone know what becomes of the LEs used for the virtual IOs when the LogicLock Region is imported into another project. Do they need to be removed or do they get removed by the compiler?

Thanks in Advance, Doug

Hi Doug,

I've had this problem before. The trick is to add a path-based assigment. See this thread:

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So for your mesher, add the path * -> * to the LogicLock region. Any fitter-created nodes will then be placed inside the LL region. I think Quartus 4.1 has a bug where having only the path-based assignment together with outputs defined as virtual pins causes the LL region to be ignored. To get around this I include the node assignment (which you've done by dragging the mesher onto the region) as well as the path assignment. I'd like to think Quartus 4.2 has fixed this so that only the path assignment is required, but I haven't tried it yet on that.

As for virtual IOs, these disappear when they .vqm is instantiated in an upper level and become wires.

HTH,

-- Pete