Any advice please.
I am creating a parallel uP interface to my fpga and i have separate 'processes' for the read and write functions. My question is : Will quartus synthesise separate address decoders - one for the read and one for the write, or is it 'clever' enough to munge the two together in the same decoder when synthesising ? (not sure of the tech term but is this resource sharing ?) Any help will be much appreciated
Unless you need to do both at once, consider procedures in the same process.
Only if your code tells it to.
Learn simulation.
-- Mike Treseler
Quartus II 4.0 (which is in manufacturing as I write this) has this option. It is called Auto Resource Sharing and needs to be turned on. The default value is off. This option is accessed through the Assignment->Settings->Analysis & Synthesis Settings->More Settings dialog.
The help for this option says: "Allows the Compiler to share hardware resources among many similar, but mutually exclusive, operations in your HDL source code. If you enable this option, the Compiler will merge compatible addition, subtraction, and multiplication operations. By merging operations, this may reduce the area required by your design. Because resource sharing introduces extra muxing and control logic on each shared resource, it may negatively impact the final fmax of your design."
- Subroto Datta Altera Corp.
Thanks for the response guys
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