I created a simple Verilog-2001 test-module:
`default_nettype none module top #( parameter integer D_W = 16 ) ( input wire sel, input wire signed [D_W-1:0] ina, inb, output wire signed [D_W:0] out );
assign out = sel ? (ina - inb ) : (ina + inb); endmodule // : top `default_nettype wire
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When I ran this module through Xilinx Webpack 10.1, it synthesized as a "addsub" macro. I.e., I tested another module which performs addition-only, and both modules occupied the same amount of LUT. Furthermore, the Xilinx synthesis report even tells me :
| "Synthesizing Unit . | Related source file is "top.v". | Found 17-bit addsub for signal . | Summary: | inferred 1 Adder/Subtractor(s). | Unit synthesized. | | INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing."
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But I tried the same top.v module in Altera Quartus-II. I manually turned ON 'auto resource sharing' inside the Project Analsyis settings.
When I synthesize to (Cyclone-II 2C20), Quartus-II creates an adder unit, plus a bunch of separate muxes in front of port 'inb.' I've found that the LUT consumption is TWICE the amount (34 vs 17) as a straight adder-only.
| Resource Usage (my "addsub") | Estimated Total logic elements 34 | | Total combinational functions 34 | Logic element usage by number of LUT inputs | -- 4 input functions 0 | -- 3 input functions 16 | --