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Quartus-II 7.2sp1 and Systemverilog Assertion SVA?

I tried synthesizing a Systemverilog-RTL file in Quartus-II 7.2sp1. The synthesis-engine doesn't seem to understand SVA (systemverilog assertion) syntax.

property prop_x; @ ( posedge clk ) // disable iff (rstn) (!$stable( comb_sm )) |-> ##1 (comb_sm !== BADSTATE); endproperty : prop_x

ap_x: assert property( prop_x );

For now, I've simply put some `ifdef/`endif blocks around the SVA, to conditionally remove it from Quartus-II compile.

Now, I assumed SVA was standardized along with the rest of Systemverilog, and synthesis-tools are supposed to ignore the SVA-constructs -- i.e. ugly `ifdef should not be needed.

Is this understanding correct? For example, does Synopsys Design Compiler and Cadence RTL Compiler require `ifdef blocks around SVA?

Reply to
aka
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It Depends!! Yes the SVA constructs are a standard just like the SVD constructs. But that does not mean the tools fully understand the SystemVerilog language.

Your tool vendor should have a list that breaks down thier SystemVerilog support by LRM section. I know that the tools I work with are only partially literate in System Verilog.

Some of the tools don't support the entire SVD constructs yet, let alone the SVA constructs. Even if this means just to ignore them as unsynthesizable.

Reply to
Dwayne Dilbeck

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