I've tried using the "interface" construct in a Quartus-II project, but I can't tell if it's working the way it is supposed to. I tried declaring an interface like the following:
interface interface_cpu_vgachar_vga( input logic [15:0] cpu_addr, input logic cpu_write, input logic cpu_read, input logic [15:0] cpu_wdata, output logic [15:0] cpu_rdata ); endinterface // : interface_cpu_vgachar_vga
interface interface_cpu_vgachar_cpu( output logic [15:0] cpu_addr, output logic cpu_write, output logic cpu_read, output logic [15:0] cpu_wdata, input logic [15:0] cpu_rdata ); endinterface // : interface_cpu_vgachar_cpu
When I use either interface as a top-level port, Altera's pin-assignment menu lists them as 'bidir'. And the synthesis-logfile shows a bunch of warnings like this: Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus if_cpu.cpu_rdata[0]~15 that it feeds Warning: The bidir "if_cpu.cpu_wdata[0]" has no source; inserted an always disabled tri-state buffer.
What am I doing wrong?