Hi, I've been getting some strange behaviour compiling hierarchical vhdl files in quartus. The code is a vhdl reworking of the pong.v & vga files from fpga4fun.
When written as separate files with a top level .bdf or with a top level .vhd instantiating the other files as components or any other variation of multple files fails to synthesise correctly.
Regardless of which variation of the above is tried, it always synthesises the same component.
When written as a single .vhd file with a .bdf for the pin connections it synthesises correctly.
the initial structure of the files was
top-level.bdf-| | pong.vhd------| | hysnc.vhd-+
hsync was a dependency of pong.vhd and was the only code that would actually be synthesised when the compiler focus was set to the top-level .bdf in spite of the synthesis tool reporting 'found 2 design units in pong.vhd' etc,etc.
compiling/sysnthesising pong.vhd on its own results in no errors.
Having googled without finding a solution, does anyone have any suggestions. ( other than sticking with verilog :) as it's for a student exercise)
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