Hi,
I am facing a strange problem while doing Synthesis P&R of a logic on "Excalibur" device (Altera EPXA10F1020C1 Package FBGA1020) using "Quartus 4.0".
The logic written in Verilog is as below:-
--------------------------------------------------------- always @(negedge ResetN or posedge Clk1) begin:logic1 if(ResetN == 1'b0) begin delayedReadyN1