I'd love if someone could tell me if what I've found is as stupid as I think it is, or far cleverer than I am.
So I'm putting together a design using Qsys on Quartus 13.0. I used the Avalon-MM Clock Crossing bridge out of the Altera library, and have been having some wacky issues on reset. So I go spelunking.
The Avalon-MM Clock Crossing bridge wraps two of the Avalon-ST Dual Clock FIFO. Okay, I suppose that makes sense. Both these cores have two reset inputs, one for the master/write side clock and one for the slave/read side. Fine, sure, good.
In the ST FIFO that's at the core of all this, however, those two resets never meet up. So the write side reset asynchronously clears the write_ptr, and the read side reset async clears the read_ptr.
Well, now I know why I'm getting old junk transactions stuck in my clock crossing bridge after resetting one side. Does anyone have a reason why one might want to reset only one side or the other of the FIFO, or is this (undocumented, of course) behavior just silly?