QII simulation annoyance

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Many of the nodes I want to probe seem unavailable in the simulation.
They are either optimized away, or refuse to show up in the simulation
window even when selected in the vwf.

Is there a way to prevent this from happening such as a setting an
optimization level or marking registers so they will be available?

thanks


Re: QII simulation annoyance
Are you talking about functional simulation of your code,
rtl functional simulation or rtl timing simulation ?

Rgds
AndrE9%


Re: QII simulation annoyance
I see only two types of simulation in QII, functional and timing. I have
tried both, and they both have this problem. The project I am trying to
simulate has both verilog and VHDL files. It is a subset of the entire
project, so I just take the part I want to simulate and create a new
project around it. I don't have a .pin file. Do I need one?

In the node finder, I can search for registers or 'design entry' to see
all objects. Many of the objects I select for my vwf will not show up in
the subsequent simulation, even for functional simulations.

It sure seems like an optimization thing, since I can make the problem
signals probe-able by tying them to known working outputs. There is also
the problem of having nodes renamed so they are not recognizable. Isnt
there a 'debug' mode of simulation that will preserve all nodes?

snipped-for-privacy@web.de wrote:
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Re: QII simulation annoyance
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For complex designs, it is common practice
to write HDL source and simulate *that* using
a vhdl simulator, before running Quartus.

        -- Mike Treseler

Re: QII simulation annoyance



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Sounds like a good thing to do. Which tools provide this 'source level'
simulation? Any free ones?

thanks


Re: QII simulation annoyance
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You should be able to download a free version of ModelSim from Altera's
web site.

-a


Re: QII simulation annoyance
The approach I've taken is to add pins to get the desired signals to
appear as module ports.  This works great if I'm simulating sub sets of
the final design.   And in the total design these pins will eventually
get optomized away.

If you get to the top level and need to see pins then you need to get
then to output pins on the device.  If you're out of pins I put them
into a mux and this will keep the signals available for viewing.

This all works great for functional simulatins.

Good Luck.
george


Re: QII simulation annoyance



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OK, but what about when the signal looks OK in the sim, but it does not
appear on the chip?


Re: QII simulation annoyance
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Maybe it got optimized away for a reason?

-a


Re: QII simulation annoyance


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Maybe so, but why does the sim say otherwise? I thought the whole point of
doing a timing simulation was to know exactly how it would behave. Of
course my test vectors might not reflect real life.






Re: QII simulation annoyance
Hi George,

I do the same thing in my designs as you do but when I am out of pins,
I use the "Virtual pin = 0n" attribute in quartus.

These pins can be imported in Modelsim like a physical device pin.

Greetings
Markus


GMM50 schrieb:
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Re: QII simulation annoyance
See http://www.altera.com/support/kdb/2003/05/rd05142003_7103.html

It describes how to use the "keep" attribute to preserve a combinational
node, and the "preserve" attribute to preserve a register.  If you set the
appropriate attribute on a node, it will prevent the optimization algorithms
from removing it, even if that would result in a more efficient circuit.
Hence you can select and view it in a simulator after compilation (either
functional or timing simulation).  As some other posters have pointed out,
you can also bring the signal out to a pin, which is an indirect way of
forcing it to be preserved -- this is often less convenient in a large
design, however.

See the Quartus online help for examples of the precise syntax to use to set
these attributes.

Regards,

Vaughn
Altera
[v b e t z (at) altera.com]

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Re: QII simulation annoyance
This is useful, but not what I need right now. I am now faced with the
problem of having a good timing sim, but a non-functioning design.
Essential signals that appear OK in the sub-project sim are being
removed somehow when I compile the whole project. What would cause the
sim results to be incorrect?

I have a verilog top module which contains both verilog and vhdl
modules. Is there some strange rule about connecting ports when mixing
language modules? I am only having problems with the vhdl outputs.



Vaughn Betz wrote:

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Re: QII simulation annoyance
Can you clarify what is happening?

Are you saying that when you simulate a subdesign, or the whole design, all
its outputs look OK, but when you run the entire design in hardware it
doesn't work?  Or are you saying that when you simulate the whole design the
simulation does not pass, even though the components worked?

The likely problems are different in those two cases.

Vaughn
Altera
[v b e t z (at) altera.com]

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