Hi, I am new to VHDL. I write the following simple counter program in ISE webpack 8.2. Both two can be behavior simulated. But, the simulation of the second (without Reset control) is not correct after synthesis. This example is just an exercise to me. What I care is: Is there other pitfalls I have to know in order to avoid it cannot synthesis?
Thank you very much.
-- First architecture Behavioral1 of smallComp is
--signal clk: clk in std_logic; signal count : INTEGER range 0 to 15; begin cp1: process (clk, RESET) begin if RESET='1' then count = 15 then count