QDR II SRAM Interface

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I am currently designing a circuit with a Virtex 4 FX FPGA and QDR I
memory chip operating at 250MHz. I have  a couple of questions :-

1) Can someone give me some advice regarding the decoupling capacito
requirements? I have had a look around the web but there seems to be
lack of info.

2) Can I get away with no termination? The longest track will be aroun
1.5". I have looked at a micron app note reagrding DDR2 and they stat
that for DDR2 around 2" is the max without termination. But as this is
different memory I am not sure if this would be valid.



Re: QDR II SRAM Interface

some comments, below:

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I am presuming you mean the QDR memory bypassing.  I can't help you
there.  The FPGA bypassing is covered in:


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A number of customers do their SI simulations, and discover they are
able to use LVCMOS 6 or 8 mA fast IO, and they meet all requirements
(HSTL to LVCMOS, or SSTL to LVCMOS does work, but you need to simulate
it, first.  1.5" might be OK, and then again, it might not).


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