PWM, PLD programming ,(up/down ramp frequency)

Not sure I get the question about a single pin on the 20V8, but generally speaking

- variable reluctace motors are like coarse stepper motors, so will need a circular pole pattern driving - best derived from a single PAL/GAL, using something like CUPLs State engine Sequence statement

$DEFINE Phase1 'b'00010000

Sequence ReluctanceDrive { PRESENT Phase2 If Hold NEXT Phase2; IF !Hold & CW NEXT Phase3; IF !Hold & !CW NEXT Phase1; .. repeat here.. } Missing states in a Sequence statement will jump to 'b'00000000, due to the D FF's used, so you need to include exit from this state.

Soft start is an issue of 'how soft' ?

For a Wide dynamic range stepper design, we used an Exponent/mantissa approach in a CPLD. ( you would need multiple 20V8's )

In this, octaves, or 2:1 freq prescaler ranges are done with a simple tapped divider - a single 20V8 would cover maybe 7 octaves, with a 3 bit 'exponent pointer' or MUX selector to choose which Freq is OP.

Because 1 sudden 2:1 freq jump is likely too much, you apply this in front of a stage that divides by 32..64, or 64..128, or 128..256 etc ( call this the mantissa PLD ) - resolution is 5 or 6 or 7 bits

Ramp DOWN in freq then occurs by increasing the divider in the Mantissa, until you get to MAX, and then next step is add-in /2, and jump back to MIN divide. Each Octave is then covered 32 or 64 or 128 steps etc

Not sure how you want to set the soft start, but one simple scheme would be to have a QuadEncoder driving a Up/Dn SPEED counter, that indexes into the 2 plds above.

All up, the full Motor Control system would have ~4 SPLDs [ 22V10's might be better ask your tutor about 22V10's ? ] ATF22V10CQZ is a good candidate.

- Motor Field State engine

- Octave Divider, eg 7 octaves, so has 3 index bits

- Mantissa Divider, eg 32..64, so has 5 index bits

- UpDn speed counter, with 3+5 bits output, and SIGN/DIRN, maybe with a RESET to Zero 'panic button' :)

- optional LED Decoders to show what speed you have dialed up to.

-jg

Thanks for your response and I'm sorry about my vagueness about certain points, what I meant by a single pin output, is that this single output from my frequency ramp CPLD would be the clock source for another CPLD which would contain the three pole switching sequence (this bit I've managed to do), it is this sequencing frequency that I have hopes of using to control the motor speed.

This assignment has been previously undertaken successfully, with using only two of the 20v8 devices and this is what where actively encouraged to limiting ourselves to.

I suspect the softstart to be much cruder than the type you have suggested (which is probably the correct method).

In your reply you mention a "tapped divider, exponent pointer, or Mux selector" could you possibly suggest an example of how these are coded in cupl.

Below is an extract of coding for the switching (which is just a re-worked up down counter)

/** Inputs **/ Pin 1 = clk ; Pin 2 = FWD ; Pin 3 = REVER ; Pin 4 = STOP ; pin 11 = !OE; /** Outputs **/ Pin [16..18] = [Q2..0]; /** **/

/** Declarations and Intermediate Variables **/ field srcont = [Q2..0]; $Define S0 'b'000 $Define S1 'b'001 $Define S2 'b'010 $Define S3 'b'011 $Define S4 'b'100 $Define S5 'b'101 $Define S6 'b'110

field mode = [FWD,REVER,STOP]; /* declare mode control field

*/ up = mode:4; /* define srcont up mode */ down = mode:2; /* define srcont down mode */ clear = mode:[3,5,7]; /* define srcont clear mode */

/** Logic Equations **/

Sequenced srcont { /* running srcont */

present S0 if up next S1; if down next S1; if clear next S0; present S1 if up next S5; if down next S3; if clear next S0;

present S5 if up next S4; if down next S2; if clear next S0;

present S4 if up next S6; if down next S6; if clear next S0;

present S6 if up next S2; if down next S4; if clear next S0;

present S2 if up next S3; if down next S5; if clear next S0;

present S3 if up next S1; if down next S1; if clear next S0;

Thank you Stewart

Somewhere you have to generate the clock to determine the Step freq. If that is external, from a SigGenerator or similar, then you need a way to proportionally gate that.

Look into Rate Multipliers : These have Fo = N/Base output, so a 4 bit binary one can start at 1/16 fi, and step thru 2/16,3/16 up to 16/16 Fi, in linear frequency steps

Rate Multiplier info is not easy to find, so here is one ref :

Then the 4 Bit number that feeds this Rate Multiplier, could derive from a saturating counter (one that counts to a MAX, and then stops until reversed. ) The step rate of the RateNumber determines the soft-start, so you could clock that from the Phase signals, or a divided version of the phase signal for slower still Start-rate. ( so far, you have used only 3 bits of the PhaseGen PLD)

- this will give a revolution proportional slow start, which may be too conservative at very low step rates, but it is simple, and you can fit both the 4 bit rate Multiplier Ctr, 1 rate MergeCell, the 4 bit saturating Ctr, Delayed Dirn BIT, and your 3 bit phase engine into 2 PLDs.

The Delayed Dirn bit is some fine-tuning, that would only allow DIRN to be changed ONLY at the LOWEST possible rate value.

-jg