Putting the Ring into Ring oscillators

Just a silly thought - how about using a very long async delay path as a memory device - like the mercury delay-line memories of olden times . Not useful but maybe an interesting exercise for those with too much time on their hands....

Jim,

the idea itself is not really new. Indeed, it is well known to the community of people beeing interested in picosecond time resolution measurements. I have used a chain of 32 "carry-elements" (extremely fast interconnections between logic elements to make the carry bit move fast enough for long adders. a.s.o.) to construct a 110 ps resolution time interval counter with a ALTERA 10K30 gate array. If you want to use things like that seriously, keep in mind that the unit delays are highly dependand on chip temperature and supply voltage. There are some tricks available to remove theses dependancies or correct for them. For commercially available chips using such technology have a look at

Regards Ulrich Bangert

"Jim Granville" schrieb im Newsbeitrag news: snipped-for-privacy@clear.net.nz...

device - like the

interesting exercise for those

It's tricky. If the process doesn't have exactly equal rise and fall times, duty cycle changes as the sig propagates, so either 1's or 0's get narrower and narrower until one of them disappears.

There are TDC chips that use a long string of buffers to generate a lot of successive delays. They usually servo Vcc of the string to keep the overall delay and symmetry on target.

John

Jim Granville schrieb:

No. The article is not talking about chained buffers for high timing resolution. Such a setup would still charge the clock lines from VDD and discharge to GND for each clock cycle.

They are really talking about sending a wave around a transmission line. Standing wave clocking is an exotic but established technique in PCB design. At high frequencies you can use it inside ICs. A physical wave uses the same charge again and again, only resistive and EMI losses need to be refreshed by buffers PARALLEL to the transmission line. Also, there is virtually no clock skew.

Kolja Sulimma

Correct - see my comment on using the routes inside a FPGA for this.

yes, Parallel drive might test the FPGA tools some more :)

Series drive would be a compromise, where the physical delay dominates the gate delay. With each generation, the gate delays shrink faster than the physical delays.

-jg

Jim Granville schrieb:

I believe you are still missing the point. If you are chaining buffers you are still fully charging and discharging each node in each clock cycle using the power supply. That is not a wave.

The same energy is traveling back and forth (for standing waves) or in a circle (for circular waves). You only need to replace some damping effects (Resonance). You definitely did not do that in a CPLD.

You cannot have the energy cross FET-gates. At least not at frequencies that low so series will achieve nothing.

Kolja Sulimma

Correct.

Correct

No, if you thought that was what I was claiming, then sorry.

Interesting - shame there is no Freq/Temperature or Freq/Vcc info. Have you ever seen that for these circuits ?

The Freq of this wave osc is dominated (but not wholly determined by) by the length-transit times. It will have some dependance on Vcc, as the drivers (even parallel) will load and thus shift the frequency.

Bringing this back into the FPGA domain:

The idea is to build the closest thing a FPGA fabric allows. Use the routing path-lengths to dominate the delays, and place the (series) buffers only sparingly. The result should be a Physical Ring Osc, where the Physical ring dominates, and thus gives better precision. With each FPGA generation, the buffer effects will decrease.

-jg

Jim Granville schrieb:

Hmm. Probably currently the RC-Delay of the wires will dominate. At least R is not well controlled. But for large chips you start seeing inductive effects inside large ICs, and then you might be right.

Kolja