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pulse generation using SRL16E on a Virtex-II

Hi all,

I'm using the code below to generate a pulse which is 16x57600 from a

51.2 MHz clock signal to controll the sampling in a rs232 module. The pulse generator does not work however. It generats a constant high signal instead of a 921.6 kHz pulse.

Can anyone see what might be faulty with my design? I'm clueless...

/Johan

library IEEE; use IEEE.std_logic_1164.all;

library unisim; use unisim.vcomponents.all;

entity baud16 is port( Clk : in std_logic; baud_pulse : out std_logic); end entity baud16;

architecture imp of baud16 is

attribute BOX_TYPE : string; component SRL16E is -- synthesis translate_off generic ( INIT : bit_vector := X"0000" ); -- synthesis translate_on port ( CE : in std_logic; D : in std_logic; Clk : in std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; Q : out std_logic ); end component SRL16E; attribute BOX_TYPE of SRL16E : component is "BLACK_BOX"; component FD is port ( C : in std_logic; D : in std_logic; Q : out std_logic); end component FD; attribute BOX_TYPE of FD : component is "BLACK_BOX";

signal clkdv56 : std_logic; signal clkdv56_i1 : std_logic; signal clkdv56_i2 : std_logic; signal clkdv56_i3 : std_logic;

-- signal clkdv14_4 : std_logic; signal baud_pulse_i : std_logic; begin

--Denna SRL dividerar inklockan med 14 Del_8 : SRL16E --synthesis translate_off generic map ( INIT => X"0000") --synthesis translate_on port map ( CE => '1', -- [in std_logic] D => clkdv56, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '0', -- [in std_logic] Q => clkdv56_i1); -- [out std_logic]

Del_16_1 : SRL16E --synthesis translate_off generic map ( INIT => X"0000") --synthesis translate_on port map ( CE => '1', -- [in std_logic] D => clkdv56_i1, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '1', -- [in std_logic] Q => clkdv56_i2); -- [out std_logic]

Del_16_2 : SRL16E --synthesis translate_off generic map ( INIT => X"0000") --synthesis translate_on port map ( CE => '1', -- [in std_logic] D => clkdv56_i2, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '1', -- [in std_logic] Q => clkdv56_i3); -- [out std_logic]

Del_16_3 : SRL16E --synthesis translate_off generic map ( INIT => X"0001") --synthesis translate_on port map ( CE => '1', -- [in std_logic] D => clkdv56_i3, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '1', -- [in std_logic] Q => clkdv56); -- [out std_logic]

DFF : FD port map ( C => Clk, -- [in std_logic] D => clkdv56, -- [in std_logic] Q => baud_pulse); -- [out std_logic]

end architecture imp;

Reply to
Johan Bernspång
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"Johan Bernspång" wrote

Hi Johan,

the SRL16E components in your design are not initialized for synthesis. Dependent on your synthesis tool, either delete the "synthesis translate_on/off" lines or add attributes with INIT values for the SRL16E components.

Hope this helps, Michael

Reply to
Michael Rhotert

Tjena Johan,

You can't directly connect the output from on SRL16 to the next one. It only works for the first SRL16.

The other SRL16 will have it's output high for many clock cycles which creates the constant high signal. For the other SRL16, you need to clean the signal to only be high for one clock cycle.

Göran Bilski

Johan Bernspång wrote:

Reply to
Goran Bilski
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Hi,

Instead of you spending time creating the code, I have attached some modules.

The baud_rate module will produce the signal that you want. The module is however a little more flexible and allows you to specify the ratio that you want to divide the incoming clock. The module will find all the factors between 2-16 which makes up the ratio. The problem is when the ratio is a prim number and thus can't be split up into factors. The module will then return to a standard counter for implementing the function.

For some application, the ratio doesn't need to be exact and there are some inaccuracy allowed. UARTs has this flexibility. So you can specify an inaccuracy which allows the modules to search for values around the ratio which can be split into factors.

The cleaning of the signal for the SRL16 can be done in a LUT (you need an AND gate) but I have used two DFFs for doing the same function in order to save some LUTs.

The code is a good example of what VHDL can do.

Göran

Johan Bernspång wrote:

Reply to
Goran Bilski

Goran,

thanks a lot for such an interesting example of VHDL power. I couldn't care less for a baudrate generator, but I liked a lot the way it's handled. Very clever.

BTW, with default stated generics it compiles with XST (6.1SP3) in 3 slices in a Spartan III.

I had to comment out the "library opbxxxx" lines, tough.

Thanks again!

Have you some other more ? ;-))

Reply to
Antonio Pasini
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Hi,

Glad that you liked the code. I think it's showing the power of a programming language like VHDL.

Yes, I have more code but that is MicroBlaze and I can't send out that. ;-)

Göran Bilski

Ant>>Instead of you spending time creating the code, I have attached some

Reply to
Goran Bilski

Hey Goran, How about posting the code direct. Not all of us have news hosts that can pass on attachments! Ta, Syms.

Reply to
Symon

..or maybe a couple of links into a Xilinx.com\comp.arch.fpga.Date.ID.YGTI.. one link could be vanilla text, and one html syntax highlighted (many editors now have a save-as html option), and you can also copy/paste from a web browser into a text editor, and keep just the code. This also allows bookmarking, and avoids anyone bleating about bandwidth usage...

I presume everyone can web-link from their news readers OK ?

-jg

Reply to
Jim Granville

Or, just wait till the end of the month when it will turn up in the archive at

formatting link

Philip

=================== Philip Freidin snipped-for-privacy@fpga-faq.com Host for

formatting link

Reply to
Philip Freidin

Ok,

Here is the two files inlined.

Göran

-------------------------------------------------------------------------------

-- $Id: divide_part.vhd,v 1.2 2003/02/13 16:13:28 goran Exp $

-------------------------------------------------------------------------------

-- divide_part.vhd - Entity and architecture

--

--
***************************************************************************
--  **  Copyright(C) 2003 by Xilinx, Inc. All rights 
reserved.               **
Reply to
Goran Bilski

more info on such circuits:

formatting link

Reply to
Yttrium

Johan,

Since it looked like this thread has side-tracked a little, I wanted to follow up on the original code as it was not too bad, just a few mistakes. I took out the attribute and component declarations which are not necessary if you include the library UNISIM and use UNISIM.VComponents.all statements and removed all of the translate_off and translate_on's and the implpemented code worked just like the behavioral simulation did. I do not think there was an inherent problem with this code other than the fact that you were using the transalte_off/on's in the code and the SRL was not getting intitialized properly because of it. At the speeds you are talking about, the code should run fine, as-is but if you did need speed, you could use SRLC16's which use a dedicaed net for cascading that runs faster and you could have the feedback path to the intitial SRL in the chain derived from the register as the clock-to-out of the register is faster than the SRL but as I said, at 51 MHz, probably not necessary.

I will attach your modified code below for refernce.

-- Brian

library IEEE; use IEEE.std_logic_1164.all;

library unisim; use unisim.vcomponents.all;

entity baud16 is port( Clk : in std_logic; baud_pulse : out std_logic); end entity baud16;

architecture imp of baud16 is

signal clkdv56 : std_logic; signal clkdv56_i1 : std_logic; signal clkdv56_i2 : std_logic; signal clkdv56_i3 : std_logic;

-- signal clkdv14_4 : std_logic; signal baud_pulse_i : std_logic; begin

--Denna SRL dividerar inklockan med 14 Del_8 : SRL16E generic map ( INIT => X"0000") port map ( CE => '1', -- [in std_logic] D => clkdv56, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '0', -- [in std_logic] Q => clkdv56_i1); -- [out std_logic]

Del_16_1 : SRL16E generic map ( INIT => X"0000") port map ( CE => '1', -- [in std_logic] D => clkdv56_i1, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '1', -- [in std_logic] Q => clkdv56_i2); -- [out std_logic]

Del_16_2 : SRL16E generic map ( INIT => X"0000") port map ( CE => '1', -- [in std_logic] D => clkdv56_i2, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '1', -- [in std_logic] Q => clkdv56_i3); -- [out std_logic]

Del_16_3 : SRL16E generic map ( INIT => X"0001") port map ( CE => '1', -- [in std_logic] D => clkdv56_i3, -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => '1', -- [in std_logic] A1 => '1', -- [in std_logic] A2 => '1', -- [in std_logic] A3 => '1', -- [in std_logic] Q => clkdv56); -- [out std_logic]

DFF : FD port map ( C => Clk, -- [in std_logic] D => clkdv56, -- [in std_logic] Q => baud_pulse); -- [out std_logic]

end architecture imp;

Reply to
Brian Philofsky

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