Hi, Spartan3 does have internal pullup and pulldown resistors on all its I/O. I'll work with LVCMOS33. I have to communicate with a DSP in a serial mode both during configuration (master serial) and while working after the FPGA has been programmed. I was supposed to bring the CCLK (clock during configuration) and the serial_clock signals from the FPGA on an AND port in order to use the same pin of the DSP for the clock in the 2 situations. Could I set low the HSWAP_EN during configuration to pullup the serial_clock (which is on a user pin, global clock) and then, after its completition, bring the CCLK at a high logic level with the CclkPin Bitstream option? Do these setting use internal pullups? When can I use a internal pullup and when should I place an external one? Thanks, Marco
- posted
18 years ago