Pull up resistors on Spartan 3 mode pins

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
People here are driving me crazy insisting that the Xilinx factory has
told them that you *MUST* tie the mode pins to either Vaux or GND.
After finding all the info in the data sheet and talking with support,
it looks pretty clear to me that the S3 parts have a very stiff
internal pull up and there is no need for an external pull up of any
kind, resistor or direct connection to Vaux.

Am I misunderstanding?  Why did the factory tell us before that the
mode pins *MUST* be tied to Vaux?  Did we misunderstand what they were
saying?

I promise this is the last time I will ask about this.  I am totally
sick of going around this loop with everyone here.


Re: Pull up resistors on Spartan 3 mode pins
by stiff mean smaller pullup value than 47-100kohm?

if that so then its something that is not well known - ASFAIK no FPGA
have stiff pull's before (or after configuration).

Antti


Re: Pull up resistors on Spartan 3 mode pins
Quoted text here. Click to load it

Antti,

Read the Spartan-3 data sheet.  It's been known to many engineers for quite
some time that user-definable pullup and pulldown resistors are much stiffer
than other gens.  Spartan3E "fixed" those excessive values, returning to
something more moderate.

I just wish *I* had an answer for rickman.

- John_H



Re: Pull up resistors on Spartan 3 mode pins
what you mean by 'user-defineable' rickman was talking about
'pre-configuration' mode pull-ups and those can not be user defined?

Antti


Re: Pull up resistors on Spartan 3 mode pins
I think Steve Knapp explained:
The "weak" pull-ups got too strong in S3, but they are now again made
properly in S3E.
Some people in Xilinx are overly concerned about the weakness, and thus
the danger of crosstalk into these pins.
Sometimes this paranoia leads to strong statements like "must".

BTW, it is very easy to measure the resistor value: just short-circuit
the pin to ground with a multi-meter.

With lower supply voltages, lower thresholds and sometimes higher
leakage currents, we all have to get away from the idea of 50 to 100k
resistors.1k to 3.3 k are more meaningful values for external resistors
that are supposed to define a level (unless it would affect power in
ultre-low power designs)
PeterAlfke, Xilinx


Re: Pull up resistors on Spartan 3 mode pins

Quoted text here. Click to load it

Design the PCB with options for SMD resistors, that can also be
0-Ohm shunts, and say 'define in production for valid logic levels'.
That gets you past the design review, and closes the case :)

-jg



Re: Pull up resistors on Spartan 3 mode pins
Quoted text here. Click to load it

I started the design review process with pullups and pull downs of 10
kohms and was told I had to use direct connections.  Of course they
could have been replaced with 0 ohm resistors at any time if needed.
Once I had researched the issue, I thought I had an FAE's blessing of
4.7 kohm resistors.  I had found that the pull up resistors were rather
strong in the S3 parts, but did not find any indication that there were
internal pullups on those pins.  Turns out I had missed the sentance
that told about them.  Once I found that, it all started to make sense.
 With internal pullups of 1-3 kohms I can see where a pull down
resistor would have to be low enough that there would not be much point
of using a value larger than 0 ohms.  Being very cramped for space,
especially in the area of the mode pins, I removed the pullups all
together and am relying on the internal pullups.  But some people here
("here" my work, not "here" the newsgroup) just won't let go of the
bone.  They are insisting that the pins must be connected to Vaux
directly because of what they were told a year ago.

I don't want to put parts on the board that aren't required.  It seems
pretty durn clear to me that pullup resistors are not needed on the
mode pins at any time, under any circumstances.  The board is due to
come out of layout in a couple of days and I don't want to interrupt
progress.  I don't understand why I can't get a clear answer to this
question.  Peter replied, but didn't answer the question.  I honestly
do not trust the support phone line (because I don't actually talk to
the person who gives the answer, just the gopher who relays the
message) and can't document what I am told verbally.  I can't get an
account to work to get support by email.  So I guess I'll have to
resort to working with the FAE who has already given me bad advice.


Re: Pull up resistors on Spartan 3 mode pins
For crying out loud, do not make a federal case out of this!

If the documentation asks for a short circuit, then do it!
If your gut feel says there is no need for any external pull-up at all,
then measure the internal pull-up impedance the way I suggested, and if
it is below 3 kilohm, then connect nothing.
If the FAE suggests an external resistor, so use one.
This may be a question of belts or suspenders or both or neither...

But remember: If you want to establish a logical Low level, you must
definitely be cautious and measure whether you are fighting an internal
pull-up.

I much rather spend 10 minutes with a multi-meter than indulge in
contankerous debates in the newsgroup.
We are all engineers and not scribes, aren't we?

Peter Alfke, obviously somewhat irritated...
Like Austin, I am human, too.
Even though we always wear the Xilinx badge, we are still allowed to
voice an opinion...


Re: Pull up resistors on Spartan 3 mode pins
The documentation DOESN'T say to strap unless you think a schematic in
an app note is definitive direction on how to treat those pins.

The engineers are bugging rickman because of app notes they saw that
showed direct connects.

The documentation does not clearly state the condition of the pullups
for dedicated inputs like the JTAG lines that I couldn't get to work in
a chain for the life of me a few months ago.

There have been repeated attempts to clarify the datasheet information
on this board without a clear answer - it's clear that he needs to email
Steve Knapp directly but that certainly won't help me without follow up
here.

This is not a federal case and I have been impressed with the civility
demonstrated by rickman and Austin.

Steve Knapp hasn't appeared to answer the question most explicitly posed
by Rickman as a clarifying question.

Gut feels do not work when an engineer has to submit to a design review
process that doesn't allow "gut feel" for a documented follow up to a
design review action item.

The FAE suggested a resistor which isn't compatible with the Spartan-3
configuration.

Multimeters work for one part, not for a production design.
____________

I may be asked to consider a Spartan3 as opposed to the 2 big Spartan3Es
on my one board - if I have to go that route I'll be facing the same
documentation and the knowledge that there hasn't been a clear answer
here in these threads.

All that's desired is a straight answer - is that so much to ask?


Peter Alfke wrote:
Quoted text here. Click to load it

Re: Pull up resistors on Spartan 3 mode pins
John, this is analog territory, and there is NOT just ONE right answer.

Obviously, a short circuit will always work, if you never need the pin
for any other purpose.
   But we will not force you to do that, since you may have reasons not
to like it. It's a free country!
   There is no mystery here, the purpose is only to establish a High
logic level. Nothing more, nothing less.
Obviously, a built-in pull-up resistor will establish a High logic
level, but it might be sensitive to crosstalk coming from your
pc-board..
Obviously, any external resistor reduces the pull-up impedance, and
improves the situation.
Obviously an external pull-down resistor must be low enough in value to
overcome the internal pull-up resistance.

And I still favor a multimeter for getting a grip on fundamentals.

I am all for clear documentation, but it never hurts to keep the
engineering mind alive.
Compared to multi-gigabit receiver issues, this mode-pin level debate
is really a trivial subject.

Peter Alfke


Re: Pull up resistors on Spartan 3 mode pins

Quoted text here. Click to load it

Wasn't there some question on just WHEN these pullups are 'alive' ?
- a multimeter is not going to be much help there....  :(

But a simple table in the data sheet, giving defined values, for
all phases of Config state (includes Vcc's ), and what is needed
(or not needed) for a legal logic condition, should nail it ?

-jg



Re: Pull up resistors on Spartan 3 mode pins
Jim, please give us the benefit of the doubt, that we are not totally
stupid.
The mode pins are of interest at the very beginning of the
configuration process.
That's obviously when the pull-ups are active.
I do not know when they are being de-activated, but trust us that they
are active when it matters.
We have 22 years experience in this technology, and have shipped many
hundreds of millions of FPGAs...
But you are right, there is always an opportunity for better
documentation.
Remember: This whole lengthy discussion never mentioned a technical
problem or malfunction, only a diversity of suggestions, all of them
correct.

Peter Alfke, Xilinx, from home


Re: Pull up resistors on Spartan 3 mode pins

Quoted text here. Click to load it

Where did I claim that ?

Quoted text here. Click to load it

Just to remind you - the audience, here is not you, Austin, Rickman,
etc, ( we ALL know 'it works' ) but those in rickman's reference :

" But some people here ("here" my work, not "here" the newsgroup) just
won't let go of the bone.  They are insisting that the pins must be
connected to Vaux directly because of what they were told a year ago."

ie they are saying to him : 'Prove it'.
He is asking for Xilinx to help him do that.

-jg




Re: Pull up resistors on Spartan 3 mode pins

Quoted text here. Click to load it

Lilliput in Gulliver's Travels comes to mind - wars fought over whether
to break boiled eggs at the big or small end!

Leon


Re: Pull up resistors on Spartan 3 mode pins

Quoted text here. Click to load it

But is that if externally strapped to ground as someone at the factory
appears to have informed rickman's group or unconnected such that the
internal pullups guarantee operation all the time?

Quoted text here. Click to load it

The discussion has a technical problem as the source.  His steps may be
slightly different but in my ISO9000 dictated compliance from years ago,
if a design review produces an action item that says "check if the mode
pins must be strapped to the rails directly because I saw that done on a
Xilinx official application note" then that item must be followed up
with a documented response providing evidence to address the original
concern.

This technical problem - guaranteeing the design will operate as
expected to the satisfaction of picky reviewers - cannot be addressed
with the information at hand either through the data sheets, the FAE
(incorrect info - we're all human), or through this forum.

Quoted text here. Click to load it

- John Handwork
Exclusively Xilinx for 8 years now

Re: Pull up resistors on Spartan 3 mode pins

Quoted text here. Click to load it

Not if you are not doing multi-gigabit receivers.  The longer design
review issues go unresolved, the greater the probability they start
reaching non-engineering minds.  You do not want "help" from these people!


    ~Dave~

Re: Pull up resistors on Spartan 3 mode pins

Quoted text here. Click to load it

Well said :) A little knowledge is a dangerous thing...

-jg


Re: Pull up resistors on Spartan 3 mode pins
Responses embedded - this is to underscore why I don't believe the
information has been adequately digested, not because I feel an
arguement is necessary.  Trivial aspects of the design are not properly
documented - that's been admitted - but the corrections have not been
brought to our attention.  So - trivially - what *did* I need to know
about the JTAG interface that would have saved about 50 engineering
hours and a change to a board that would have gone through a spin
anyway?  I'd sure like to know in case I end up designing with that part
instead of the two XC3S1600Es on an upcoming board.

Peter Alfke wrote:
Quoted text here. Click to load it

This could be digital territory but the analog aspects - pullups that
are unaffected by HSWAP_EN - are forced upon the designers for pins -
such as the JTAG - that no engineer should suspect would be pulled up by
the silicon.

Quoted text here. Click to load it

And the Spartan3 devices have an explicitly low pullup impedance that
should be virtually immune to any crosstalk that's applied to an
unconnected pin.  I'd expect the antenna of connecting a 10 kohm
resistor to the internal 3 kohm pullup would introduce more noise than
leaving the pin unconnected.

Quoted text here. Click to load it

A multimeter is nice if a board that *isn't* strapped to VCC or GND is
readily available - not usually the case when someone's designing their
first board with this series of devices - but it still provides only an
order of magnitude idea of what's happening on the pin.  Tolerances on
pullup and pulldown currents don't need to be tight so they aren't.  I
*will not* design a production board that relies on measurements to
determine acceptable operation.  The silicon *must* be tested to analog
parameters that will guarantee operation in the board environment I
design to.

Quoted text here. Click to load it

An engineering mind is of little use when you have to submit to a design
review with other engineers - some of which haven't designed with the
device or know the documentation as thoroughly as someone who has - and
must have documentation to support any action items produced from the
review.

Quoted text here. Click to load it

Trivial subjects deserve trivial answers.  There have been no answers
that I have seen in these threads.
_____

Will the mode pins which appear to always have external pullups
independent of the HWSWAP_EN pin behave fine when no external resistors
are connected?  Will the ~3kohm equivalent pullup impedances in
unconnected pins work *just as well* or better than an external 4.7kohm
pullup resistor to an imaginary mode pin with no internal pullup?

If the answer is "sure, no problem" where do we assure the fellow
engineers that the pins will behave properly on power up (e.g., once the
POR thresholds are passed, will those internal pullups have the full
logic level established with internal pullups)?  Is there a design issue
such that POR from external pullups of nominal impedance willnot produce
valid operation?  Where could I possibly devine what the minimum
pulldown resistor is to establish guaranteed behavior allowing an
external jumper to change the mode pins?

These are trivial issues.  With no documented answers.  The last request
from rickman was specifically - quoted in full:

rickman wrote:
 > People here are driving me crazy insisting that the Xilinx factory has
 > told them that you *MUST* tie the mode pins to either Vaux or GND.
 > After finding all the info in the data sheet and talking with support,
 > it looks pretty clear to me that the S3 parts have a very stiff
 > internal pull up and there is no need for an external pull up of any
 > kind, resistor or direct connection to Vaux.
 >
 > Am I misunderstanding?  Why did the factory tell us before that the
 > mode pins *MUST* be tied to Vaux?  Did we misunderstand what they were
 > saying?
 >
 > I promise this is the last time I will ask about this.  I am totally
 > sick of going around this loop with everyone here.

Do you believe that the trivial answer *has* been fully illustrated by
Steve Knapp or others in these threads?

There isn't a great desire to spend time and attention to trivial
matters when there are problems like Multi-Gigabit transceivers out
there.  If we lose the trivial details, we lose the ability to design
for error free production because of trivial misunderstandings.

All ricman wants is to get the fellow engineers off his back on a
trivial issue.  All I want is an understanding of how the pins behave
that I connect for "trivial" functionality such as the JTAG pins that I
*could not configure* to operate as part of a chain - I had to give the
Spartan3 its own chain.  The problems I had are probably trivial but I
was unable to work past them without extreme measures.

Re: Pull up resistors on Spartan 3 mode pins
Peter-

Quoted text here. Click to load it

I think that type of thinking shows a problem.  Engineers can't use
your devices if they a) can't trust your documentation, b) can't get a
straight answer from Xilinx experts to augment the documentation in an
official and formal manner that stands up to design review, and c) have
to spend weeks messing around with configuration just to get the part
up and running before they can even try advanced features.

I would turn this around and say:  if you can't handle basic
configuration issues, then how can you be trusted to handle MGT issues?

What happens when you next decide that inner workings of a BUFGMUX are
"trivial"?  I can't get a straight answer on that either.

I always worried important Xilinx people were thinking like this.
Please I hope it's not really the case.

-Jeff


Re: Pull up resistors on Spartan 3 mode pins
Let me repeat:
If you want a mode pin to be interpreted as all High, you can do one of
three things, and all are correct:
1. do nothing
2. use external pull-up of any value
3. strap to Vcc

If you want a mode pin to be interpreted as Low, do one of two things:
1. strap to ground
2. use a resistor of 330 Ohm or lower to ground.

The mode pins have an internal pull-up resistor during configuration.
Once  the FPGA has been powered up, and the configuration memory has
been cleared, the INIT pin goes High, and this Low-to-High transition
on INIT samples the levels on the mode pins. At any other time,
(earlier or later) the levels on the mode pins are irrelevant to the
FPGA configuration process, or to its operation.

For people who prefer not to think, we can also be dictatorial:
"You must strap mode pins to either Vcc or ground."
It sure works 100% of the time, but it is not the only possible way.

This has been described in many generations of Xilinx data books, ever
since I was responsible for them in the late 'eighties and early
'nineties, and the behavior of the mode pins never changed in our
18-year history.
Peter Alfke


Site Timeline