PSL pros and cons

Hi KVM,

From my limited exposure to the language (I've just done an introduction course),

Pros:

1) Very powerful formal language, or assert statement on steroid for hardware engineers :-) 2) Easy to learn, most of the constructs are logical. 3) Most EDA vendors seem to support it. 4) There are even some vendors which can translate your embedded PSL constructs into hardware monitor. 5) PSL can be embedded in your code (hardware engineer) or put into a separate vunit (verification engineer). 6) PSL is a full formal language, a subset can be used in dynamic simulation.

Cons:

1) Only supported by high-end $$$ EDA tools (like Modelsim SE) which will limit its uptake. 2) During my PSL course I felt that I needed another language to check my PSL. 3) Easy to create spaghetti code (unreadable constructs). 4) Requires a different mindset, i.e. engineer who do not use assert statements (other than to stop the simulator) or never heard of OVL will not use it. 5) They created different flavoured version for VHDL and Verilog, so you can not write generic PSL. It shouldn't be too difficult to write a translator between the two flavours but I have seen it yet. 6) Some EDA vendors only support the Verilog flavour

If you want to learn language, get yourself onto a PSL course to make sure you learn how to think in PSL, secondly get yourself a tool which can generate VHDL from a drawn waveform, this will enable you to create simple stimulus for your PSL assertions. Get Ben Cohen's book,

I definitely like the language and will use it for my next design,

Regards, Hans.

I recommend that you read the postings on the

and in particular, "Cost of ABV insertion vs Traditional verification methods"

That posting had 700 views, and has useful info about assertion-based verification vs traditional methods discussed by engineers. Ben

----------------------------------------------------------------------------- Ben Cohen Trainer, Consultant, Publisher (310) 721-4830

snipped-for-privacy@aol.com snipped-for-privacy@mobile.att.net for Wireless messages < 110-char Author of following textbooks:

• Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition,

2004 isbn 0-9705394-6-0

• Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn

0-9705394-2-8

• Component Design by Example ", 2001 isbn 0-9705394-0-1

• VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn

0-7923-8474-1

• VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn

0-7923-8115

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