We currently have a Spartan 3 FPGA in our design. In our design, we are using two DCM's specifically. One is driving an off-chip ADC and the other is driving an FPGA register (which registers the data coming back from the off-chip ADC). One clock is manually phase-shifted at synthesis relative to the other clock to resolve clock skew issues between the ADC processing of the data and the output of the ADC being latched into the register. The clock signal to the ADC can be phase-shifted to bring the overall timing within constraint.
This setup works so far, but the question is whether it will continue to work as the FPGA temperature changes, and over variations between different chips or slight variations in the voltage supplies. The DCM driving the ADC is physically placed far from the pin which it drives. The routing from DCM to pin is accomplished via hex lines and combinational logic. Are there any general rules which are capable of predicting the sensitivity of propagation delay to temperature, voltage, and chip variations?