1. Home
  2. Field-Programmable Gate Arrays
  3. project validation: best procedures?

project validation: best procedures?

Hi,

We're trying to move our development and testing of VHDL code towards an automatic testing and validation system. Here's the idea: if I change something in the code, I would run something that would compile and test the whole thing and give an alarm if something else broke. I'm curious as to what you guys in the industry use. An obvious approach would be to build a very thorough test vector file and run it every time and look for mismatches between expected data and actual results. Is this the best approach? How about running it automatically? Do you have any ideas/experience on this matter that you could share?

Thanks in advance,

Emanuel

Reply to
Emanuel Machado
Loading thread data ...

Step one is to start using source control: CVS, subversion etc. Step two is to write a script that checks out everything into an empty directory and generates a Makefile for sim and/or synth, does a make, and runs some vsim command on the top entity. Step three is to run the script continuously and make the log files available to anyone interested.

-- Mike Treseler

Reply to
Mike Treseler

If you can afford it have a look at equivalence checkers, relative easy for RTL RTL and an absolute pain to do between gatelevelRTL. Equivalence checkers are formal tools (hence the $$$$), so no testvectors and the comparison is exhaustive. Another much easier and cheaper solution is to use waveform compare, run 2 simulation and compare the outputs, this can be done automatically and scripted by most simulators (I use Modelsim),

Hans

formatting link

Reply to
Hans

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.