Hi
I have a problem with using "IBUFG" and "RAMB16_S9" in Project Navigator (ISE 6,3), when implementing.
In VHDL, BRAM and IBUFG were just instantiated. When VHDL-simulating in modelsim, it was okay using UNISIM.
When synthesizing with XST, no errors are found but following warning messages are seen.
------------------------------------------- WARNING:Xst:766 - c:/xilinx/work/TOP.vhd line 79: Generating a Black Box for component . . . WARNING:Xst:790 - c:/xilinx/work/MODULE.vhd line 127: Index value(s) does not match array range, simulation mismatch. . .WARNING:Xst:766 - c:/xilinx/work/BLOCK.vhd line 81: Generating a Black Box for component . . . WARNING:Xst:753 - c:/xilinx/work/RAM.vhd line 176: Unconnected output port 'DOP' of component 'RAMB16_S9' . .
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Finally MAPPING errors are found as follows
------------------------------------------- ERROR:Pack:1234 - F5 mux symbol "AA_Mmux_data_inst_mux_f5_26111" drives more than one F6 mux symbol, including symbol "BB_Mmux__n0024_inst_mux_f6_10". An F5 mux may drive at most one F6. Please correct the design.
----- INFO:LIT:95 - All of the external outputs in this design are using slew rate limited output drivers. The delay on speed critical outputs can be dramatically reduced by designating them as fast outputs in the schematic. INFO:MapLib:562 - No environment variables are currently set. INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFG symbol "CLK_bufg" (output signal=clk_int2)
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Can someone help me with this troubleshooting? Thankyou in advance