Programmable pulse generator

U?ytkownik snipped-for-privacy@hotmail.com napisa?:

Hi,

I can do it for you. Let me know how you want to set parameters - parallel interface to microcontroller , microprocessor or serial controll ?

Adam

I would recommend a synchronous design using clock enabled counters.

The RTL example "clk enabled counters" here:

is not a pulse generator, but it does demonstrate square waves of three frequencies.

-- Mike Treseler

If you want to do it yourself, are you doing schematic, Verilog, or VHDL? For the guts you just want a counter that runs from one to your period-1 (after which it rolls back to 0) and a comparator for the number of cycles for your output pulse high. The registered comparator output give you a nice, clean, programmed pulse.

If you had a 100 MHz source, 10 us would require a count to at least 999 or

10 bits. This 10-bit counter also needs two 10-bit values, one for the period and one for the high width. The 10-bit comparator should implement nicely in the CPLD. The two 10-bit values need to be written into the CPLD in some form. If your load signal is asynchronous, be aware that changing the setting may present an unexpected glitch or runt pulse. Let us know if you need to avoid a single bad pulse when changing settings.

Also, do you have more than 32 Macrocells to work with and want more bells and whistles?

Where are you struggling ?

For a single pulse, you need a saturating, Reloadable counter - one that loads, counts, then stops when it hits some limit - Commonly 0000.

10us from 40ns is appx 8 bit counter. ( 10-12 bits if you load with BCD thumbwheels)

For linear frequecy rep-rate, that's not quite as simple as normal /N is a 1/X curve. Choices are a small ROM ( OK for a few Freqs), or a Rate Multiplier or DDS frequency scheme. With a Rate Multiplier, run it from max Clk, and post-scale to the <

10KHz re-trigger frequency you want, to reduce jitter.

Do you mean 1KHz to 10Khz, or 1Hz to 10Khz ? - former is one decade of Prog Fo, doable in 4 bits of RateMult, latter is 4 decades, so needs appx 14 bits binary, or 20 bits if you load with BCD thumbwheels. 10Khz to 25Mhz of postscale is ~11 bits binary.

Another pulse-generator approach, is to define the ON and OFF times, then you have just one timing chain, which is a reloadable counter, from two alternating set-values.

That's simple logic, but more set-point wires, or you could choose to compile-in the settings, and use the ISP cable to set. [ Smaller CPLD and less wires ]

-jg

A perhaps better approach is to use a loadable down-counter that is one bit wider than your maximum count. That way, the terminal count is just the MSB of the counter, and it can be used to disable the count as well. This eliminates the comparator.

A DDS can be used to get a programmable rate that is not an integer multiple of the clock frequency and that has a linear relationship between the program value and the output frequency. The DDS is basically just an accumulator to which a fixed increment is added on each clock cycle. The square-wave output is taken from the MSB of the accumulator. (It will have jitter of up to a clock cycle depending on the increment value).

Thanks for all the useful replies!

I think I need to clarify my setup... I have a small microcontroller that generates a PWM signal and I was planning to use this as the repetition rate. Also attached to the uC is an LCD and keypad to enable the user to enter the pulse width and rep rate. I'm ok with that and it works well.

At the minute I'm using a Altera Max epm7128slc84-10 which has 128 macrocells. I'm really new to all this so I have been using the schematic design entry tool. So far I have managed to use two 74160 decade programmable counters to divide my clock, the counters are controlled by the microprocessor. This approach fails because the duty cycle of the divided clock isn't 50% and I still don't know how to get a single pulse from the train of pulses?

By the way, my first approach was to use a Pic & DDS I put the idea on hold as I can't make PCB's and the DDS is surface mount! Also I'm learning much more doing this via CPLD as I've never used anything like it before.

Thanks for the help,

Jim W.

OK, so this is a uC augmented by CPLD, which is a good combination.

You need to make a 'digital monostable' - start the counter on an edge from the uC PWM, and then stop, and hold until the next trigger edge, after NNN clock cycles.

Taking your 74160, you need a JK FF, driving the 160.ClockEnable Setup an edge detector ( one clock pulse wide ) from the PWM, and The JK FF is set on this, the same one-clock pulse does the SyncLoad of the

160s. Then the terminal count from the 160, clears the JK FF, which holds everything paused, until the next Edge. The JK ff gives a variable width wide pulse.

Use a common clock for the PLD and uC, to avoid clock race conditions.

I prefer Bresenhams algorithm for frequency generation. The N-bit accumulator has a frequency error of up to 1/2^N. Bresenhams algorithm is exact for the question "generate N pulses in M clock cycles". I also has minimum jitter (up to half a clock cycle). The hardware implementation is simple and small.

Kolja Sulimma

I have't heard of that... could you post some links?

Thanks,

JW

Hmm, Hadn't thought of that. I've used Bresenham's algorithm for other things, but not for frequency generation. Should work quite well though. A DDS also solves the N pulses in M clock cycles, but only for the case M=2^k where k is the number of bits in the accumulator. I.e. the DDS produces N pulses in 2^k clocks where k is the width of the accumulator and N is the increment value. In the end, I think for M a power of two, the math reduces to the same thing whether you use Bresenham's or a DDS.

Bresenham invented famous algorithms for efficiently drawing lines and circles on bitmaps. The point here is to realized that the line drawing algorithm can be used for any kind of scaling with factors less than one. Bresenhams algorithm computes when you need to go up when drawing a line X pixels to the right and Y pixels up. This is the same problem as producing Y pulses in X clock cycles. Or scaling a bitmap by a factor Y/X. Or....

The algorithm is really simple: eps = X; while(true) { wait_for_clock_edge(); eps -= Y; if (eps < 0) { generate_pulse(); eps += X; } }

Kolja Sulimma

This is getting a little off topic but it's such fun:

I like to change the nature of the DDS and perform an N pulses in M clocks without the 2^k restriction by normally adding N in a k-bit accumulator but adding N-M in the one cycle when the accumulator overflows. The N or N-M value selection can be programmed as two constants and easily selected between the two within the accumulator. The result is typically much better available resolution. Most fractional values have an N/M solution using k values much lower than 32 bits that give accuracy significantly better than

1/4 ppb. Beyond finding the near perfect ratios (which is algoritmically straight-forward but extra software) not all N/M values have a better solution than N/2^k such that large values of k are sill desired for generic solutions.

The accumulator output range is [N-M,+N) for an accumulator that selects between the two add constants. If the range [-M,0) is preferred, Acc+N and Acc+N-M adders can be muxed to the accumulator registers based on the +N add's carry output making things like lookup tables easier to deal with. In both cases, one of the strong uses of a DDS - indexing into a lookup table with the DDS MSbits - is twisted by a range that's no longer [0,2^k). In those cases the lookup table could be adjusted to the desired range or the modified DDS range multiplied by 2^p/M for a p-bit lookup.

Because of some of the extra hardware or reduced lookup resolution, this approach is most desireable when lower jitter solutions are desired for a PLL-filtered output, keeping the jitter at the higher frequencies where they can be filtered out. There are still a few frequency values that will be problematic so it's not a complete fix.

- John_H

Hi Jim,

This is really simple stuff to do in programmable logic. You can do it with an adder, plus a comparator if your duty cycles is not 50/50. Simple in uC too, maybe even cheaper, but 10ns is probably a little too fast for a uC.

While they can be much more complex and are not working at the same frequency range, you can steal some ideas from music synthesizers and such.

- For a simple solution, check out this link:

- A more complex one is the implementation of the SID chip (MOS-6852?) [see jester_sid_voice.vhd.], found in the classic C-64 computers:

Now, If that's too much for you, I am sure someone in the NG can provide you some working code if you ask politely :)

ok, I have two other things to say: 1. Instead of paying 99 USD for a CPLD, you could pay 99-150 USD and get a very nice FPGA board, maybe even one with a *hint* PLL *hint*! Play with it, and use it in future projects. 2. Ignore that BS you read in sci.elec.design, Altera Quartus rocks. And no, it has no difficulties inferring tri-state buffers :)

and wellcome to the w> Hi All,