Programmable frequency synthesizer with Xilinx DCM

I'm sorry if this is a trivial question, but I haven't found anything on this topic in the Xilinx site: is it possible to implement a programmable frequency synthesizer with Spartan3 DCMs? With "programmable" I mean programmable at runtime (just like you can do with a programmable PLL synthesizer), not just at design time.

Thank you!

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asd
Reply to
dalai lamah
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Yes, it can be done, but it's far more flexible to use Direct Digital Synthesis to generate arbitrary frequencies over a very wide range. Here is the description of a Frequency Synthesizer that we recently built 250 copies of. Very popular in our lab and with FAEs. We are looking at the next generation going to a few GHz using MGT outputs. Fun project...

Xilinx Programmable Clock Source, Product Description

Outputs:

2 SMA connectors: LVDS, 440 mV diff., +1.20 V common mode, 1 Hz to 640 MHz 1 SMA connector: LVCMOS33 single-ended, limited to < 80 MHz

Performance: Frequency range: 1 Hz to 640 MHz, 1 Hz resolution over full range Frequency indication: 9-digit LCD display Frequency accuracy and stability: < 2ppm Cycle-to-cycle jitter:

Reply to
Peter Alfke

asd,

In the Spartan 3, or 3E, there is no ICAP interface to reprogram the DCM while in operation. In Virtex 4, there is not only the ICAP interface, but also the DRP (dynamic reconfiguration port) for the DCM which allows you to change settings.

The DCM must be reset after the constants are changed, however.

This can also be done by reconfiguration, but I am concerned that for Spartan 3, this also does not work well, as the parts will be interrupted completely while reprogramming, wheras the Virtex parts can be reprogrammed while still operating.

Austin

dalai lamah wrote:

Reply to
austin

Hi Peter,

Does it have a Spartan or a Virtex inside?

Best regards,

Ben

Reply to
Ben Twijnstra

Present generation: Spartan3 plus external PLL for higher freq. and less jitter.(

Reply to
Peter Alfke

Sounds great - any photos ?

Why stop at 1Hz ?

What about sine output, at lower frequencies ?

-jg

Reply to
Jim Granville

Peter -

Are you going to do an app note on this? Sounds like a neat project and a neat tool.

John Providenza

Reply to
johnp

Jim, I'll send you a photo.

1 Hz could easily be extended to 1 mHz or lower. Why? There are several BRAMs left over for sine-wave table-lookup. PWM output or separate D/A? Who wants it, for what?. It comes in a pretty and rugged Al-case, size of a cigarette pack (in case you remember...) Peter
Reply to
Peter Alfke

Because it's a generator, and one never knows when a slow stimulus is needed :) [The real world does not stop at 1Hz]

Or sigma-delta DAC ?

It would need to be 'all in the FPGA' as that's part of the appeal.

Maybe an external SPCO analog SW [~SOT23], for low noise Ref and low noise floor.

Audio generation is an obvious area, and with effort, it should be possible to get very low distortions, or > 90DB SFDR.

-jg

Reply to
Jim Granville

Hi Peter Alfke,

Reply to
Ben Twijnstra

Ben, I started out with "all in the FPGA". Then I found out that the $5.- LCD diplay has its own built-in micro, and the 1 ppm oscillator costs more than the FPGA, as do case and power supply together. As does the pc-board with the regulators. That's were I became pragmatic and decided to design something useful first, FPGA-centric second. That's also the answer to Jim's suggestion. How many people need ultra-pure sinewaves at ultra-precise and ultra-low frequency?

Most of our boxes get used as LVDS clock sources between 50 and 500 MHz, where they are an ideal fit. Peter Alfke

Reply to
Peter Alfke

That's the best approach - a significant use of these is for education, and if you can "show what's possible" with external PLL, and what is also possible without it, that's worth quite a lot to designers.

That would depend on how seriously you wanted to court Audio designers.

If they are not on your radar, then there is probably still an educational element of "showing what's possible" again, and having a crack at seeing what noise/distortion floor you can achieve - again with some off-fpga help, like an analog switch for the Switching DAC integrator.

-JG

Reply to
Jim Granville

Peter, Have you designed your own DDS or reused Xilinx free core? I am not familiar with this core yet, so I am not sure of what it's capable of. I assume it does not allow you to produce 1Hz to 640MHz, that's why your design is unique. Or if it does, then I guess it's unique in a way that it fits in a small box and has low clock jitter.

Reply to
bobrics

"DDS" is really just a simple (but long) accumulator, 27 bits long in my case, and there would be no problem making it 10 bits longer, getting down to one millihertz. I did not use any core for that, it's trivial. All the user- and display interface is done with Ken Chapman's PicoBlaze (thanks, Ken!). The trickery is in reducing jitter from the inherent 6 ns (one internal clock period of 160 MHz) to the more acceptable

Reply to
Peter Alfke

Hi Peter,

Oh, no sweat, really.

It's just that the description you initially gave gave me the distinct impression that you said you could do the That's were I became pragmatic and decided to design something useful

This reinforces my idea that answer 2 might not be that wrong ;-)

Best regards,

Ben

Reply to
Ben Twijnstra

Here is part of the secret: The Spartan3 actually reduces the jitter down from the fundamental +/-

3 ns ( from the 160 MHz clocking of the DDS accumulator) to 300 ps. I then use the external PLL to multiply the frequency to max 640 MHz, and also to reduce the jitter to 85 ps.

The secret sauce in Spartan3 is a hidden (undocumented) mode in the DCM that makes the DCM multiply the frequency without phase-locking the output to the input. (I do not care about phase-lock) Unfortunately (and unavoidably), this also introduces frequency wander, where many long periods (long by max 85 ps) follow each other, until they are followed by many short (by max 85 ps) periods. This wander is non-critical for testing memory interfaces or microprocessors, but cannot be tolerated as telecom references, since it looks like slow frequency drift. Next step: eliminate the wander while also reducing cycle-to-cycle jitter. There is more than hope... We learned a lot, and we have excellent instrumentation, from Tektronix and LeCroy... BTW: option #3 is not acceptable. Peter Alfke

Reply to
Peter Alfke

So, this mode is about to become documented, and user accessable ?

We wait for V2.0 :)

-jg

Reply to
Jim Granville

Marketing decided NOT to document this mode, and after detecting the hard-to-quantify wandering behavior, I gave up fighting for the release. It obviously works, but is not easy to test and support. I accept that the Southern Hemisphere will wait for V2.0, hopefully (your) early summer... Peter Alfke

Reply to
Peter Alfke

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