prog_b held low?

working with a custom board with a V4 on it. It has been working fine for a couple of months until last week - when the FPGA would just not come out of reset. I tried running a JTAG boundary scan using Impact, and got the following error:

"ERROR:iMPACT:585 - A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage. Chain TCK freq = 100000000. Chain TCK freq = 100000000. Validating chain... Boundary-scan chain validated successfully."

now it does say 'boundary-scan chain validated successfully', so whats going on here? I probed the prog_b signal on the V4 and it never goes high. There is an external pull-up on it per spec. Any ideas why the prog_b would be held low?

any help is much appreciated.

-Thanks!

Reply to
mtsukanov
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is the V4 being held in reset causing the JTAG boundry-scan to fail? or is it the other way around? There are 3 devices on the JTAG chain (PROM, CPLD and V4), so could one of the other devices be causing the V4 to be held in reset? I didn't think that would make sense. Even if the V4 doesnt get configured correctly from the PROM, it 'shouldn't' hold the prog_b low, right?? I checked the voltage ramps on the V4, looked ok.

Also I noticed the power consumption of the board increased by about

0.5W, which kind of makes me want to think theres a component failure (bad cap? bad resistor?) but again, I checked the voltage ramps and they looked fine.
Reply to
mtsukanov

are bumps allowed here? bump

Reply to
mtsukanov

well, I went ahead and took the V4 out of the JTAG chain, and the new chain consisting of just the CPLD and the PROM was recognized by Impact. Apparently the CPLD bit stream had a glitch/corruption in it, that pulled the V4's prog_b line low. Once I erased the contents of the CPLD, the V4 came out of reset.

Reply to
mtsukanov

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