Processor in CPLD

Hi.

I would like to hear your opinion on the possibility of implementing a processor in a CPLD? The functionality does not have to be greater than the old 8051 CPU, but I would like the flexibility and the possibility of adding additional logic to my design.

Has someone worked on this issue, or have an opinion on how to complete this task?

Looking forward to your replies Best Regards

Reply to
Rgr
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Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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Reply to
Uwe Bonnes

The Xilinx PicoBlaze or the open-source Mico-8 from Lattice should both be achievable in a CPLD but most CPLDs don't have memory.

While it's more of a simple FPGA than an ASIC, the Altera Max-II series of "CPLDs" has some user Flash memory available on-chip. Most CPLDs will require external memory.

- John_H

Reply to
John_H

Thank you both for your very useful replies. I can see the benefits in utilizing the Max-II series, but have they made a soft-core processor usable for these CPLD's? Like the PicoBlaze?

Best Regards

Reply to
Rgr

a

The PicoBlaze is intended for a Xilinx target. The design uses Xilinx primitives that may not map over to an Altera design. The Mico-8 is open source and does not use vendor-specific primitives.

CPLDs are typically not well suited for processor instantiation so commonly you'll only see them in FPGAs. It's because the Max-II parts are more like early FPGAs that the fit might be reasonable.

Have you considered a tiny FPGA rather than a CPLD? Having embedded RAM can really help out. If you want to access more code than would conveniently fit in the on-board RAM, you can use the same SPI flash that programs the FPGA to store additional user flash that you access through an SPI interface. Perhaps the additional flexibility from an FPGA (versus CPLD) is worth considering.

- John_H

Reply to
John_H

This one is specially designed for small CPLDs:

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You will need an external memory, however. And note that it is far simpler and more limited than a 8051.

-- Jecel

Reply to
Jecel

As an alternative to CPLDs, have you considered Actel's Igloo FPGAs? They're small-to-medium-sized FPGAs with a very low power footprint (and you can use an ARM Cortex M1 processor on it).

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K.

Reply to
Kris Vorwerk

If you have at least 65 flip flops and a few hundred gates available on your CPLD you can try:

ftp://137.193.64.130/pub/mproz/mproz3_e.pdf

Reply to
Herbert Kleebauer

We are actually doing this all the time in a course we are giving here called Digital project laboratory. The CPLDs we are using are the XC9572 and XC95108. (They are old, but they operate on 5V which is a huge advantage for us since we have many other 5V components.)

Our students commonly use two XC95108 for a complete microcoded processor. One mostly used for microcode and one mostly used for ALU stuff. Some students use many more CPLDs to implement graphics and audio as well but that is not so common.

A few students manage to fit a complete RISC-like processor into a single XC9572.

Some things to keep in mind when designing a processor (or any logic for that matter for a XC95xx-CPLD:

  • Budget your design for the number of macroblocks. One macroblock == one flip-flop plus some logic in front of it.
  • Avoid complex expressions. You will notice that especially adders can be very expensive (or constructs that infer an adder like less than or greater than). An example:

reg [7:0] counter; always @(posedge clk) begin counter 13) && (counter < 131)) begin outsignal

Reply to
Andreas Ehliar

Very important. And as you hint later, with only 36-108 flops, you can't make much of a clock divider. If you want to operate at human- visible speeds, give yourself a slow clock.

On the other hand, you can use much bigger combinatoral expressions in each macrocell of a CPLD than you can in the LUT of a typical FPGA. My experience is that you can fit a lot more logic and a lot less storage in a CPLD than you might initially expect.

You could look at my website for such an example. I fit a PCI target in a XC95108.

--
Ben Jackson AD7GD

http://www.ben.com/
Reply to
Ben Jackson

Thanks for the tips, there are some nice views among them. And thank you all for the answers - I have searched the web sites and come up with some possible solutions.

Best Regards

Reply to
Rgr

You can probably find example of Mico8 on Lattice MachXO series. However, if you want low power, using a CPLD is not a good path, and you have to add external code storage in projects of any reasonable size.

That's more power, cost, and EMC hits...

- much better to choose a small uC that has Code memory on-chip, already power-optimised, and EMC minimised!.

Use the FPGA when you have a problem you cannot solve with std devices.

-jg

Reply to
-jg

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