Process on both edges

John schrieb:

For simulation it is possible. For synthesis it strongly depends on the synthesis tool. There a few (!) synthesis toots, that support this, but most of them don't.

Using both edges of the clock is nothing else than a dual-edge flipflop. Such elements exist but they are very uncommon in standard cell libraries and FPGAs.

If you really need dual-edge behavior for synthesis (think twice about it!) you can use a pseudo dual-edge flipflop: .

Ralf

In vhdl is it possible to run a process on both edges of a clock? I tried running one if-statement on the rising edge, and one on the negative but get an timing error.

It won't synthesize. Most dual edge stuff is done at the IO pads where it is separated into single edge clock domains inside the FPGA.

It might simulate, if you post your code we'll look at it, if you're still interested.

Brad Smallridge AiVision

It can be done if invert the first clock and use that. I would still adivse against it. There really isn't a need to use both edges of a clock, it just least to buggy hard to read code. If you need a faster clock use a DCM and speed it up.

---Matthew Hicks

The following VHDL code will work in simulation. It will also work in synthesis with XST in those devices that have dual edge flip-flops in the architecture (i.e. Coolrunner). I have not tried it with synplicity.

process(vclk) begin if (vclk'event) then ... end if; end process;

This will not work with any of the Xilinx FPGAs, as there are no internal dual edge flip flops. It will probably not work on the DDR output registers, as they are not really dual edge, but rather two flops and mux.

Regards, Erik.