Hi newsgroup users,
I am trying to implement the following in my VHDL testbench:
Within a process (without sensitivity list) I call a procedure "wait_delay". In the most test cases the signal 't_order_burst_data' gets high when the procedure is left again. But there are also some cases where it gets high while the loop in the procedure is busy. I want the procedure to abort then. But how can I make the signal 't_order_burst_data' visible for the procedure all the time ?
I would be very thankful for any suggestions.
procedure wait_delay ( signal clock : std_logic; signal order_burst_data_in : std_logic) is variable i : natural; begin for i in 0 to 4 loop exit when order_burst_data_in='1'; wait until rising_edge(clock); end loop; end wait_delay; ...
process begin wait until rising_edge(t_clk); for m in 0 to 10 loop wait until rising_edge(t_clk); wait until t_order_burst_data='1'; wait_delay(t_clk, t_order_burst_data); end loop; t_continue