Problems with Xilinx Parallel III Cable

Hi,

To program my Atmel(ATmega128L) controller and Xilinx FPGA (sparta-3 XCS400) at the same time, I decided as a programmer to use the Xilinx Parallel Cable III. I implemented the programmer 100% the same as found in Xilinx's website (

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The programmer worked, but not without problems. For programming the Atmel uC I used AVRdude, and for the FPGA, ISE9.1i. The ribbon-cable from the LPT port to Programmer was 20cm long and from the programmer to the uC/FPGA board was not more than 10 cm. The problem related with this programmer were verification errors, i.e the PC can't program or read properly from the board. The interesting thing is how these verification problem came up. In the morning when I turn the PC and Board on, these verification errors are a lot. When the code that I want to download is big, its impossible to program the FPGA/uC, for small codes it works but after many tries. After 10 tries or so, the programming works correct and no verification errors no matter how many times I try to download the code or how big the code is, and this without even touching a thing on the hardware!!!

Since this problem applies to more than one board, I assume the problem must lay on the programmer itself. My explanation is that maybe the buffer IC's get hot or something...I really don't know. I want to know if there is anyone who has had problems with this programmer cable.

Thank You, JJ

Reply to
jidan1
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I'm doing exactly the same, but I'm using the Digilent Parallel JTAG3 cable ($12

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Impact 6.3 to program my Spartan3-1000, and avrdude to program my ATmega64. I had problems in the past when I had some noisy power supplies in the lab and got mysterious errors, sometimes I had to turn off the noisy power supply to make my JTAG work :)

Zoltan

Reply to
zcsizmadia

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($12

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Glad to hear that I am not the only one who has a problem with this programmer!! I thought at the beginning also it has to be some kind of interference from somewhere, but as I said, I usually change nothing, just click many times until it works, and when it does, it works without any problems for hours.But before i reach this phase, it really gives me headach :(

JJ

JJ

Reply to
jidan1

The newer Xilinx programming cables (Parallel Cable IV, Platform Cable USB) use comparators rather than simple buffers to establish proper voltage levels from the VREF pin connected to the programmer and VCC supplied eternally (keyboard passthrough or USB). The VCC supplied to the Parallel Cable III powers the buffers; the result is poor signal levels on low voltage interfaces.

I had a 2.5V JTAG interface I could not get working when using the Parallel Cable III powered by 2.5V. Just by increasing the VCC to 3.3V, I was able to keep decent logic levels and get the interface working. But I never trusted it; if I got a good result I was happy. The convenience and (decent) reliability of the Platform Cable USB is well worth the price in my mind.

- John_H

Reply to
John_H

I used 3.3V JTAG interface since the beginning, and also since the beginning I had problems with it. I think part of the problem might be in the buffer itself. The input voltage at the buffer(74HC125) used there, according to the data sheet, should be max. VCC+1.5. And if you are using VCC=3.3V or 2.5V, the high level voltage coming from the LPT(5V) will be exceeding the max. input voltage. A series resistor was used to limit the current going through the clamp didoe, however the signal might have got distorted because of that.I have also thought about using Schmitt-triggers instead of buffers. At the end I built the exact circuit posted in xilinx website, because I thought the Xilinx team knows better than me. But that circuit has caused me a lot of problems and it seems I am not the only one!

JJ

Reply to
jidan1

I've always stuck two (because they are inverting) 74HCT14 Schmidt triggers in there, and have no problems with long parallel cables on a number of different boards and computers.

Reply to
Duane Clark

May I ask why you used inverting and not non-inverting schmitt- triggers? I assume if you used inverting schmitt-triggers you would have to change the programmer software to allow these inverted signals to be understandable.

JJ

Reply to
jidan1

...or did you actually mean you used two inverted schitt-triggers becuase you didn't have one non-inverted schmitt-trigger :)

Reply to
jidan1

Yep, thats what I meant ;)

Reply to
Duane Clark

LOL...you might have not known this, but by using two schmitt-triggers (rather than one) you have made the programmer more noise immune! Do you still have the schematic for this circuit?

Reply to
jidan1

I originally got the circuit from someone here in this group (sorry, I forgot who). Anyway, here is a 60KB pdf:

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As you can see, if I have room on my circuit board, I simply stick this circuit and a connector on the board, and run a plain parallel cable between the computer and the board.

Reply to
Duane Clark

Thanks for sharing the schematics!

Hmm...the TDO and voltage sense line are the exactly the same as orginally posted by Xilinix. For the other JTAG lines (TMS, TCK, TDI), two schmitt-triggers and a buffer were used to increase noise immunity. Thats a little bit too many components for my taste, but seems to be reliable.

Reply to
jidan1

Seems to be reliable as in... you've already tried it and seen your troubles go away?

Your problem may not be on the Schmidt trigger side of your buffers but in the interface between the PC and the programmer chips.

Have you tried your existing programmer on a different PC to see if the behavior is identical or vastly different?

You could modify the Parallel-III style design with comparators and a low-voltage DC-DC boost converter with fixed 5V output to power the LPT-compatible circuit with a variable logic level I/O to get closer to Parallel-IV performance with a Parallel-III interface.

Reply to
John_H

snipped-for-privacy@hotmail.com schrieb:

As I posted before, there are many issues with parallel cable 3, especially in conjunction with old versions of impact. (The old software versions simultaneously turn of the output enable and change the data output value resulting in a race condition)

The main issue is, that the parallel port has TTL logic levels that only have a guaranteed V_OH of 2V. But a 5V powered 74HC125 has a threshold voltage of 2.5V which might never be reached. A 3.3V powered 75HC125 still has a threshold of 1.65V. In that range the slope of a parallel port output can be very slow, but the 74HC is quite fast. As a result noise on the parallel port will amplify to many clock edges to TCK.

You can solder 2k resistors between each buffers input and output pin. (0402 SMT fits perfectly) This creates a schmitt trigger with a large hysteresis which helps a lot.

For building your own cable there are CMOS families that have thresholds of 1/3 VCC instead of

1/2 VCC. A 50mV hysteresis is not enough, so you need the positive feedback from output to input in all cases.

Kolja Sulimma

Reply to
comp.arch.fpga

I have tried Parallel-III cable with 2 PC's, and with both of them this problem existed.

Reply to
jidan1

Thanks for your detailed reply Kolja, it sounds logical to me. But there is one thing still unexplained to me and that is although the Parallel-III programmer doesn't work at the beginning, when it starts to work after many tries, it continues to work for hours with no problems.Why??? It seems to me it has something to do with the temperature of the buffer IC's!

Reply to
jidan1

I have a simple upgrade to the parallel cable III that has Schmitt triggers on the clock, and a simple shunt regulator with an LED that limits internal VCC to about 4V, giving TTL compatible LPT interface even if used with 5V JTAG.

It works reliably with 2.5V to 5V JTAG chips

I have PCBs which I can send for free as long as its in the USA (1"x1" card in envelope) Requires SMT assy

Peter Wallace

Reply to
Peter Wallace

Peter Wallace wrote: ...

A combination of LVC Single Gate Schmitt Trigger and the LVC1T45 level translator also works fine

Bye

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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Reply to
Uwe Bonnes

Thanks Peter, but if you can show us the schematics that will be more than enough.

JJ

Reply to
jidan1

Where can I get these kind of comparators? What about multiple voltages? Any sample circuits I can use as a reference?

Thanks

- E.

Reply to
EvalXX

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