I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM that I want to be able to control via an FPGA on the same PCB. I am having trouble with the verilog model. I have used both a samsung and a micron model for the part (two compatible parts). Unfortunately these models are not available in VHDL, and my verilog is pretty weak.
I wondered if any one had some experience with memory models, both in terms of using them to design memory controllers and debugging them when they spit out spurious timing violations. These verilog models in particular seem to send out all manner of timing violations or functional problems that don't seem to be in line at all with what the data sheet says regarding the timing and command and control procedures (for doing a full page read or write, for instance).
Has any one else had trouble with bad/buggy models? What is the best way to solve this problem? What is the best way to go about designing a memory controller (I have seen an example on Altera's website in VHDL (but it sucks), as well as some others in open cores and one written for a homebrew graphics accelerator card (manticore). I find the documentation and/or functionality lacking in most of the aforementioned existing reference designs.
thanks